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/Zephyr-latest/boards/microchip/mec172xmodular_assy6930/support/
Dspi_cfg_128MBit.txt5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
10 BoardID = 0x316
12 [IMAGE "0"]
13 ImageLocation = 0x2000
18 SpiSignalControl = 0x00
20 ImageRevision = 0x56
21 FwOffset = 0
22 FwLoadAddress = 0xC0000
[all …]
Dspi_cfg.txt5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
14 BoardID = 0
16 [IMAGE "0"]
17 ImageLocation = 0x1000
22 SpiSignalControl = 0x00
24 ImageRevision = 0x56
25 FwOffset = 0
26 FwLoadAddress = 0xC0000
[all …]
Dspi_cfg_4MBit.txt5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
14 BoardID = 0
16 [IMAGE "0"]
17 ImageLocation = 0x100
22 SpiSignalControl = 0x00
24 ImageRevision = 0x56
25 FwOffset = 0
26 FwLoadAddress = 0xC0000
[all …]
/Zephyr-latest/boards/microchip/mec172xevb_assy6906/support/
Dspi_cfg.txt5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
14 BoardID = 0
16 [IMAGE "0"]
17 ImageLocation = 0x2000
22 SpiSignalControl = 0x00
24 ImageRevision = 0x56
25 FwOffset = 0
26 FwLoadAddress = 0xC0000
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_lpc_iocon.c14 #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
15 #define TYPE(mux) (((mux) & 0xC0000) >> 18)
17 #define IOCON_TYPE_D 0x0
18 #define IOCON_TYPE_I 0x1
19 #define IOCON_TYPE_A 0x2
27 for (uint8_t i = 0; i < pin_cnt; i++) { in pinctrl_configure_pins()
49 return 0; in pinctrl_configure_pins()
59 return 0; in pinctrl_clock_init()
62 SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);
/Zephyr-latest/dts/bindings/mtd/
Dnordic,owned-partitions.yaml22 reg = <0xe000000 0x200000>;
32 label = "image-0";
33 reg = <0xc0000 0x40000>;
45 reg = <0x100000 0x50000>;
49 reg = <0x150000 0x6000>;
56 - 0x0E0C0000--0x0E100000, with read & execute permissions, containing the
57 partition labeled "image-0".
58 - 0x0E100000--0x0E156000, with read & write permissions, containing the
/Zephyr-latest/dts/arm64/rockchip/
Drk3568.dtsi23 #size-cells = <0>;
29 reg = <0x000>;
36 reg = <0x100>;
43 reg = <0x200>;
51 reg = <0x300>;
61 reg = <0xfd400000 0x10000>, /* GICD */
62 <0xfd460000 0xc0000>; /* GICR */
82 reg = <0xfe660000 0x10000>;
Drk3399.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0x0 0x0>;
27 reg = <0x0 0x1>;
32 reg = <0x0 0x2>;
37 reg = <0x0 0x3>;
42 reg = <0x0 0x100>;
47 reg = <0x0 0x101>;
54 reg = <0xfee00000 0x10000>, /* GICD */
55 <0xfef00000 0xc0000>, /* GICR */
[all …]
/Zephyr-latest/dts/arm64/ti/
Dti_am62x_a53.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
29 reg = <0x70000000 DT_SIZE_K(64)>;
47 reg = <0x01800000 0x10000>, /* GICD */
48 <0x01880000 0xc0000>; /* GICR */
56 reg = <0x000f4000 0x2ac>;
62 reg = <0x02800000 0x100>;
73 reg = <0x02810000 0x100>;
84 reg = <0x02820000 0x100>;
[all …]
/Zephyr-latest/soc/nuvoton/npcm/common/esiost/
Desiost_args.py18 NO_VERBOSE = 0
26 …'npcm400': {'flash_address': 0x80000, 'flash_size': 0x20000, 'ram_address': 0x10008000, 'ram_size'…
55 valid_arguments = arguments[0]
/Zephyr-latest/soc/microchip/mec/common/spigen/
Dmec_spi_gen.py13 HDR_SIZE = 0x140
14 HDR_VER_MEC172X = 0x03
15 HDR_VER_MEC152X = 0x02
16 HDR_SPI_CLK_12MHZ = 0x3
17 HDR_SPI_CLK_16MHZ = 0x2
18 HDR_SPI_CLK_24MHZ = 0x1
19 HDR_SPI_CLK_48MHZ = 0
20 HDR_SPI_DRV_STR_1X = 0
21 HDR_SPI_DRV_STR_2X = 0x4
22 HDR_SPI_DRV_STR_4X = 0x8
[all …]
/Zephyr-latest/dts/arm64/nxp/
Dnxp_mimx95_a55.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
31 reg = <0x100>;
37 reg = <0x200>;
43 reg = <0x300>;
49 reg = <0x400>;
55 reg = <0x500>;
74 reg = <0x48000000 0x10000>, /* GIC Dist */
75 <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */
[all …]
Dnxp_mimx8mm_a53.dtsi25 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
68 reg = <0x38800000 0x10000>, /* GIC Dist */
69 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
77 reg = <0x30200000 DT_SIZE_K(64)>;
91 reg = <0x30210000 DT_SIZE_K(64)>;
105 reg = <0x30220000 DT_SIZE_K(64)>;
119 reg = <0x30230000 DT_SIZE_K(64)>;
133 reg = <0x30240000 DT_SIZE_K(64)>;
[all …]
Dnxp_mimx8mp_a53.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
62 reg = <0x38800000 0x10000>, /* GIC Dist */
63 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
72 reg = <0x30360000 DT_SIZE_K(64)>;
77 reg = <0x30380000 DT_SIZE_K(64)>;
83 reg = <0x30200000 DT_SIZE_K(64)>;
96 reg = <0x30210000 DT_SIZE_K(64)>;
109 reg = <0x30220000 DT_SIZE_K(64)>;
[all …]
Dnxp_mimx8mn_a53.dtsi25 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
68 reg = <0x38800000 0x10000>, /* GIC Dist */
69 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
77 reg = <0x30200000 DT_SIZE_K(64)>;
91 reg = <0x30210000 DT_SIZE_K(64)>;
105 reg = <0x30220000 DT_SIZE_K(64)>;
119 reg = <0x30230000 DT_SIZE_K(64)>;
128 gpio-reserved-ranges = <0 21>;
[all …]
Dnxp_mimx93_a55.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0x100>;
57 reg = <0x48000000 0x10000>, /* GIC Dist */
58 <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */
66 reg = <0x443c0000 DT_SIZE_K(64)>;
76 reg = <0x44480000 DT_SIZE_K(64)>;
81 reg = <0x44450000 DT_SIZE_K(64)>;
87 reg = <0x47400000 DT_SIZE_K(64)>;
[all …]
/Zephyr-latest/soc/cdns/sample_controller32/include/
D_soc_inthandlers.h97 if (mask & 0x7f) { in _xtensa_handle_one_int1()
98 if (mask & 0x7) { in _xtensa_handle_one_int1()
99 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
100 mask = BIT(0); in _xtensa_handle_one_int1()
101 irq = 0; in _xtensa_handle_one_int1()
115 if (mask & 0x18) { in _xtensa_handle_one_int1()
140 if (mask & 0x38080) { in _xtensa_handle_one_int1()
141 if (mask & 0x8080) { in _xtensa_handle_one_int1()
165 if (mask & 0xc0000) { in _xtensa_handle_one_int1()
190 return 0; in _xtensa_handle_one_int1()
[all …]
/Zephyr-latest/include/zephyr/arch/nios2/
Dnios2.h69 __asm__("mov %0, et" : "=r" (et)); in _nios2_read_et()
82 __asm__("mov %0, sp" : "=r" (sp)); in _nios2_read_sp()
104 __asm__ volatile ("flushda (%0)" :: "r" (addr)); in _nios2_dcache_addr_flush()
109 __asm__ volatile ("flushd (%0)" :: "r" (offset)); in z_nios2_dcache_flush()
114 __asm__ volatile ("flushi %0" :: "r" (offset)); in z_nios2_icache_flush()
127 NIOS2_CR_STATUS = 0,
147 * we get errors "Control register number must be in range 0-31 for
201 #define NIOS2_STATUS_PIE_MSK (0x00000001)
202 #define NIOS2_STATUS_PIE_OFST (0)
203 #define NIOS2_STATUS_U_MSK (0x00000002)
[all …]