Lines Matching +full:0 +full:xc0000
13 HDR_SIZE = 0x140
14 HDR_VER_MEC172X = 0x03
15 HDR_VER_MEC152X = 0x02
16 HDR_SPI_CLK_12MHZ = 0x3
17 HDR_SPI_CLK_16MHZ = 0x2
18 HDR_SPI_CLK_24MHZ = 0x1
19 HDR_SPI_CLK_48MHZ = 0
20 HDR_SPI_DRV_STR_1X = 0
21 HDR_SPI_DRV_STR_2X = 0x4
22 HDR_SPI_DRV_STR_4X = 0x8
23 HDR_SPI_DRV_STR_6X = 0xc
24 HDR_SPI_SLEW_SLOW = 0
25 HDR_SPI_SLEW_FAST = 0x10
26 HDR_SPI_CPOL_LO = 0
27 HDR_SPI_CPOL_HI = 0x20
28 HDR_SPI_CHPHA_MOSI_EDGE_2 = 0
29 HDR_SPI_CHPHA_MOSI_EDGE_1 = 0x40
30 HDR_SPI_CHPHA_MISO_EDGE_1 = 0
31 HDR_SPI_CHPHA_MISO_EDGE_2 = 0x80
33 # User defined constants HDR_SPI_RD_ (0, 1, 2, 3) as per boot rom spec.
38 HDR_SPI_RD_111 = 0
44 PLD_LOAD_ADDR = 0xc0000
45 PLD_LOAD_ADDR_MEC172X = 0xc0000
46 PLD_LOAD_ADDR_MEC152X = 0xe0000
47 PLD_ENTRY_ADDR = 0
52 MCHP_CHAR_P = 0x50
53 MCHP_CHAR_H = 0x48
54 MCHP_CHAR_C = 0x43
55 MCHP_CHAR_M = 0x4D
63 TAG_SPI_LOC = 0
64 HDR_SPI_LOC = 0x100
65 PLD_SPI_LOC = 0x1000
67 CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
68 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
71 'mec15xx': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 },
72 'mec172x': { 'sram_base': 0xc0000, 'sram_size': 0x68000, 'header_ver': 3 },
78 SPI_MODE_DEFAULT = 0
79 SPI_MODE_MIN = 0
86 print("{0} = {{ ".format(title), end='')
89 print("0x{0:02x}, ".format(v), end='')
90 if (count % 8) == 0:
102 crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
103 crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)])
104 return crc ^ 0x55
110 bits[23:0] = bits[31:8] of the Header SPI address
112 bits[31:24] = CRC8-ITU of bits[23:0]
115 tag = bytearray([(hdr_spi_loc >> 8) & 0xff,
116 (hdr_spi_loc >> 16) & 0xff,
117 (hdr_spi_loc >> 24) & 0xff])
118 tag.append(crc8(0, tag))
131 Payload entry point address: index 0 instructs Boot-ROM to assume
140 hdr[0] = MCHP_CHAR_P
145 hdr[4] = CHIP_DICT[chip]['header_ver'] & 0xff
156 if spi_config['spi_mode'] & 0x01:
158 if spi_config['spi_mode'] & 0x02:
160 if spi_config['spi_mode'] & 0x04:
163 # translate 1x, 2x, 4x, 6x to 0, 1, 2, 3
173 # translate "slow", "fast" to 0, 1
177 # MEC172x b[0]=0 do not allow 96MHz SPI clock
178 hdr[6] = 0 # not using authentication or encryption
191 hdr[8] = pld_load_addr & 0xff
192 hdr[9] = (pld_load_addr >> 8) & 0xff
193 hdr[0xA] = (pld_load_addr >> 16) & 0xff
194 hdr[0xB] = (pld_load_addr >> 24) & 0xff
197 hdr[0xC] = pld_entry_addr & 0xff
198 hdr[0xD] = (pld_entry_addr >> 8) & 0xff
199 hdr[0xE] = (pld_entry_addr >> 16) & 0xff
200 hdr[0xF] = (pld_entry_addr >> 24) & 0xff
204 hdr[0x10] = pld_units & 0xff
205 hdr[0x11] = (pld_units >> 8) & 0xff
206 # hdr[0x12:0x13] = 0 reserved
211 hdr[0x14] = pld_offset & 0xff
212 hdr[0x15] = (pld_offset >> 8) & 0xff
213 hdr[0x16] = (pld_offset >> 16) & 0xff
214 hdr[0x17] = (pld_offset >> 24) & 0xff
216 # hdr[0x18] = 0 not using authentication
217 # hdr[0x19] = 0 not adjusting SPI flash device drive strength
218 # hdr[0x1A through 0x1F] = 0 reserved
219 # hdr[0x20 through 0x27] = 0 not adjust SPI flash device drive strength
220 # hdr[0x28 through 0x47] = 0 reserved
221 # hdr[0x48 through 0x4F] = 0 reserved
222 # hdr[0x50 through 0x7F] = ECDSA P-384 Public key x-component
223 # hdr[0x80 through 0xAF] = ECDSA P-384 Public key y-component
224 # hdr[0xB0 through 0xDF] = SHA-384 digest of hdr[0 through 0xAF] Always required
225 # hdr[0xE0 through 0x10F] = ECDSA signature R-component of hdr[0 through 0xDF]
226 # hdr[0x110 through 0x13F] = ECDSA signature S-component of hdr[0 through 0xDF]
229 h.update(hdr[0:0xB0])
235 hdr[0xB0:0xE0] = hdr_digest
266 default=0,
283 choices = [0, 1, 2, 3, 4, 5, 6, 7],
284 default=0,
285 help="SPI signalling mode 3-bit field: 0-7")
301 help="Fill with 0xFF to flash size")
319 print(" chip = {0}".format(args.chip))
320 print(" infilename = {0}".format(args.infilename))
321 print(" outfilename = {0}".format(args.outfilename))
322 print(" SPI size (kilobytes) = {0}".format(args.spi_size_kb))
323 print(" Entry point address = {0}".format(args.entry_point))
324 print(" SPI frequency MHz = {0}".format(args.spi_freq_mhz))
325 print(" SPI Read Mode = {0}".format(args.spi_read_mode))
326 print(" SPI Signalling Mode = {0}".format(args.spi_mode))
327 print(" SPI drive strength = {0}".format(args.spi_drive_strength))
328 print(" SPI slew rate fast = {0}".format(args.spi_slew_rate))
329 print(" Verbose = {0}".format(args.verbose))
354 print("Read input FW binary: length = {0}".format(indata_len))
357 pad_len = 0
358 if (indata_len % PLD_GRANULARITY) != 0:
360 # NOTE: MCHP Production SPI Image Gen. pads with 0
367 print("Padded FW binary: length = {0}".format(indata_len))
373 …print("ERROR: FW binary exceeds flash size! indata_len = {0} spi_size = {1}".format(indata_len, sp…
377 if args.entry_point == 0:
388 print("Build Header at {0}: Load Address = 0x{1:0x} Entry Point Address = 0x{2:0x}".format(
414 # trailer[0:0x30] = SHA384(indata || ec_info_block || cosig)
415 # trailer[0x30:] = 0xFF
424 trailer[0:len(image_digest)] = image_digest
441 i = 0
443 … print("buf[{0}]: {1} location=0x{2:0x} length=0x{3:0x}".format(i, sb[0], sb[1], len(sb[2])))
448 print("len(fill) = {0}".format(len(fill)))
450 loc = 0
454 print("sb: {0} location=0x{1:0x} len=0x{2:0x}".format(sb[0], sb[1], len(sb[2])))
458 print("loc = 0x{0:0x}: Fill with 0xFF len=0x{1:0x}".format(loc, fill_len))
463 if rem > 0:
464 fout.write(fill[0:rem])
467 print("loc = 0x{0:0x}: write {1} len=0x{2:0x}".format(loc, sb[0], len(sb[2])))
476 if rem > 0:
477 fout.write(fill[0:rem])
480 print("Final loc = 0x{0:0x}".format(loc))