1/* 2 * Copyright 2022,2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <freq.h> 9#include <arm64/armv8-a.dtsi> 10#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h> 11#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a55"; 26 reg = <0>; 27 }; 28 29 cpu@100 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a55"; 32 reg = <0x100>; 33 }; 34 35 }; 36 37 arch_timer: timer { 38 compatible = "arm,armv8-timer"; 39 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL 40 IRQ_DEFAULT_PRIORITY>, 41 <GIC_PPI 14 IRQ_TYPE_LEVEL 42 IRQ_DEFAULT_PRIORITY>, 43 <GIC_PPI 11 IRQ_TYPE_LEVEL 44 IRQ_DEFAULT_PRIORITY>, 45 <GIC_PPI 10 IRQ_TYPE_LEVEL 46 IRQ_DEFAULT_PRIORITY>; 47 interrupt-parent = <&gic>; 48 }; 49 50 psci: psci { 51 compatible = "arm,psci-1.1"; 52 method = "smc"; 53 }; 54 55 gic: interrupt-controller@48000000 { 56 compatible = "arm,gic-v3", "arm,gic"; 57 reg = <0x48000000 0x10000>, /* GIC Dist */ 58 <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ 59 interrupt-controller; 60 #interrupt-cells = <4>; 61 status = "okay"; 62 }; 63 64 iomuxc: iomuxc@443c0000 { 65 compatible = "nxp,imx-iomuxc"; 66 reg = <0x443c0000 DT_SIZE_K(64)>; 67 status = "okay"; 68 pinctrl: pinctrl { 69 status = "okay"; 70 compatible = "nxp,imx93-pinctrl"; 71 }; 72 }; 73 74 ana_pll: ana_pll@44480000 { 75 compatible = "nxp,imx-ana"; 76 reg = <0x44480000 DT_SIZE_K(64)>; 77 }; 78 79 ccm: ccm@44450000 { 80 compatible = "nxp,imx-ccm-rev2"; 81 reg = <0x44450000 DT_SIZE_K(64)>; 82 #clock-cells = <3>; 83 }; 84 85 gpio1: gpio@47400000 { 86 compatible = "nxp,imx-rgpio"; 87 reg = <0x47400000 DT_SIZE_K(64)>; 88 interrupt-parent = <&gic>; 89 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 90 <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 91 gpio-controller; 92 #gpio-cells = <2>; 93 }; 94 95 gpio2: gpio@43810000 { 96 compatible = "nxp,imx-rgpio"; 97 reg = <0x43810000 DT_SIZE_K(64)>; 98 interrupt-parent = <&gic>; 99 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 100 <GIC_SPI 58 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 101 gpio-controller; 102 #gpio-cells = <2>; 103 }; 104 105 gpio3: gpio@43820000 { 106 compatible = "nxp,imx-rgpio"; 107 reg = <0x43820000 DT_SIZE_K(64)>; 108 interrupt-parent = <&gic>; 109 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 110 <GIC_SPI 60 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 111 gpio-controller; 112 #gpio-cells = <2>; 113 }; 114 115 gpio4: gpio@43830000 { 116 compatible = "nxp,imx-rgpio"; 117 reg = <0x43830000 DT_SIZE_K(64)>; 118 interrupt-parent = <&gic>; 119 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 120 <GIC_SPI 190 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 121 gpio-controller; 122 #gpio-cells = <2>; 123 }; 124 125 lpuart1: serial@44380000 { 126 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 127 reg = <0x44380000 DT_SIZE_K(64)>; 128 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 129 interrupt-names = "irq_0"; 130 interrupt-parent = <&gic>; 131 clocks = <&ccm IMX_CCM_LPUART1_CLK 0x6c 24>; 132 status = "disabled"; 133 }; 134 135 lpuart2: serial@44390000 { 136 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 137 reg = <0x44390000 DT_SIZE_K(64)>; 138 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 139 interrupt-names = "irq_0"; 140 interrupt-parent = <&gic>; 141 clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>; 142 status = "disabled"; 143 }; 144 145 lpi2c1: i2c@44340000 { 146 compatible = "nxp,lpi2c"; 147 clock-frequency = <I2C_BITRATE_STANDARD>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 reg = <0x44340000 0x4000>; 151 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 152 interrupt-parent = <&gic>; 153 clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>; 154 status = "disabled"; 155 }; 156 157 lpi2c2: i2c@44350000 { 158 compatible = "nxp,lpi2c"; 159 clock-frequency = <I2C_BITRATE_STANDARD>; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 reg = <0x44350000 0x4000>; 163 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 164 interrupt-parent = <&gic>; 165 clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>; 166 status = "disabled"; 167 }; 168 169 lpi2c3: i2c@42530000 { 170 compatible = "nxp,lpi2c"; 171 clock-frequency = <I2C_BITRATE_STANDARD>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 reg = <0x42530000 0x4000>; 175 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 176 interrupt-parent = <&gic>; 177 clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>; 178 status = "disabled"; 179 }; 180 181 lpi2c4: i2c@42540000 { 182 compatible = "nxp,lpi2c"; 183 clock-frequency = <I2C_BITRATE_STANDARD>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 reg = <0x42540000 0x4000>; 187 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 188 interrupt-parent = <&gic>; 189 clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>; 190 status = "disabled"; 191 }; 192 193 lpi2c5: i2c@426b0000 { 194 compatible = "nxp,lpi2c"; 195 clock-frequency = <I2C_BITRATE_STANDARD>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 reg = <0x426b0000 0x4000>; 199 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 200 interrupt-parent = <&gic>; 201 clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>; 202 status = "disabled"; 203 }; 204 205 lpi2c6: i2c@426c0000 { 206 compatible = "nxp,lpi2c"; 207 clock-frequency = <I2C_BITRATE_STANDARD>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 reg = <0x426c0000 0x4000>; 211 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 212 interrupt-parent = <&gic>; 213 clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>; 214 status = "disabled"; 215 }; 216 217 lpi2c7: i2c@426d0000 { 218 compatible = "nxp,lpi2c"; 219 clock-frequency = <I2C_BITRATE_STANDARD>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 reg = <0x426d0000 0x4000>; 223 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 224 interrupt-parent = <&gic>; 225 clocks = <&ccm IMX_CCM_LPI2C7_CLK 0x80 24>; 226 status = "disabled"; 227 }; 228 229 lpi2c8: i2c@426e0000 { 230 compatible = "nxp,lpi2c"; 231 clock-frequency = <I2C_BITRATE_STANDARD>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 reg = <0x426e0000 0x4000>; 235 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 236 interrupt-parent = <&gic>; 237 clocks = <&ccm IMX_CCM_LPI2C8_CLK 0x80 24>; 238 status = "disabled"; 239 }; 240 241 lpspi1: spi@44360000 { 242 compatible = "nxp,lpspi"; 243 reg = <0x44360000 0x4000>; 244 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 245 interrupt-parent = <&gic>; 246 status = "disabled"; 247 clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 }; 251 252 lpspi2: spi@44370000 { 253 compatible = "nxp,lpspi"; 254 reg = <0x44370000 0x4000>; 255 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 256 interrupt-parent = <&gic>; 257 status = "disabled"; 258 clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 }; 262 263 lpspi3: spi@42550000 { 264 compatible = "nxp,lpspi"; 265 reg = <0x42550000 0x4000>; 266 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 267 interrupt-parent = <&gic>; 268 status = "disabled"; 269 clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 }; 273 274 lpspi4: spi@42560000 { 275 compatible = "nxp,lpspi"; 276 reg = <0x42560000 0x4000>; 277 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 278 interrupt-parent = <&gic>; 279 status = "disabled"; 280 clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 }; 284 285 lpspi5: spi@426f0000 { 286 compatible = "nxp,lpspi"; 287 reg = <0x426f0000 0x4000>; 288 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 289 interrupt-parent = <&gic>; 290 status = "disabled"; 291 clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 }; 295 296 lpspi6: spi@42700000 { 297 compatible = "nxp,lpspi"; 298 reg = <0x42700000 0x4000>; 299 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 300 interrupt-parent = <&gic>; 301 status = "disabled"; 302 clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 }; 306 307 lpspi7: spi@42710000 { 308 compatible = "nxp,lpspi"; 309 reg = <0x42710000 0x4000>; 310 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 311 interrupt-parent = <&gic>; 312 status = "disabled"; 313 clocks = <&ccm IMX_CCM_LPSPI7_CLK 0x6c 0>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 }; 317 318 lpspi8: spi@42720000 { 319 compatible = "nxp,lpspi"; 320 reg = <0x42720000 0x4000>; 321 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 322 interrupt-parent = <&gic>; 323 status = "disabled"; 324 clocks = <&ccm IMX_CCM_LPSPI8_CLK 0x6c 2>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 }; 328 329 flexcan1: can@443a0000 { 330 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 331 reg = <0x443a0000 DT_SIZE_K(64)>; 332 interrupt-parent= <&gic>; 333 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 334 <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 335 interrupt-names = "common", "error"; 336 clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; 337 clk-source = <0>; 338 status = "disabled"; 339 }; 340 341 flexcan2: can@425b0000 { 342 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 343 reg = <0x425b0000 DT_SIZE_K(64)>; 344 interrupt-parent= <&gic>; 345 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 346 <GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 347 interrupt-names = "common", "error"; 348 clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; 349 clk-source = <0>; 350 status = "disabled"; 351 }; 352 353 edma4: dma@42000000 { 354 compatible = "nxp,edma"; 355 reg = <0x42000000 (DT_SIZE_K(64) * 32)>; 356 valid-channels = <0>, <1>; 357 interrupt-parent = <&gic>; 358 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 359 <GIC_SPI 128 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 360 #dma-cells = <2>; 361 status = "disabled"; 362 }; 363 364 sai3: dai@42660000 { 365 compatible = "nxp,dai-sai"; 366 reg = <0x42660000 DT_SIZE_K(64)>; 367 mclk-is-output; 368 clocks = <&ccm IMX_CCM_SAI3_CLK 0x0 0x0>; 369 clock-names = "mclk1"; 370 interrupt-parent = <&gic>; 371 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 372 dai-index = <3>; 373 dmas = <&edma4 0 60>, <&edma4 1 61>; 374 dma-names = "tx", "rx"; 375 status = "disabled"; 376 }; 377 378 enet: enet@42890000 { 379 compatible = "nxp,enet1g"; 380 reg = <0x42890000 DT_SIZE_K(64)>; 381 clocks = <&ccm IMX_CCM_ENET_CLK 0 0>; 382 status = "disabled"; 383 384 enet_mac: ethernet { 385 compatible = "nxp,enet-mac"; 386 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 387 interrupt-names = "COMMON"; 388 interrupt-parent = <&gic>; 389 nxp,mdio = <&enet_mdio>; 390 nxp,ptp-clock = <&enet_ptp_clock>; 391 status = "disabled"; 392 }; 393 enet_mdio: mdio { 394 compatible = "nxp,enet-mdio"; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 status = "disabled"; 398 }; 399 enet_ptp_clock: ptp_clock { 400 compatible = "nxp,enet-ptp-clock"; 401 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 402 interrupt-parent = <&gic>; 403 clocks = <&ccm IMX_CCM_ENET_PLL 0 0>; 404 status = "disabled"; 405 }; 406 }; 407 408 tpm1: tpm@44310000 { 409 compatible = "nxp,tpm-timer"; 410 reg = <0x44310000 DT_SIZE_K(64)>; 411 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 412 interrupt-names = "irq_0"; 413 interrupt-parent = <&gic>; 414 clocks = <&ccm IMX_CCM_TPM1_CLK 0 0>; 415 prescaler = <1>; 416 status = "disabled"; 417 }; 418 419 tpm2: tpm@44320000 { 420 compatible = "nxp,tpm-timer"; 421 reg = <0x44320000 DT_SIZE_K(64)>; 422 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 423 interrupt-names = "irq_0"; 424 interrupt-parent = <&gic>; 425 clocks = <&ccm IMX_CCM_TPM2_CLK 0 0>; 426 prescaler = <1>; 427 status = "disabled"; 428 }; 429 430 tpm3: tpm@424e0000 { 431 compatible = "nxp,tpm-timer"; 432 reg = <0x424e0000 DT_SIZE_K(64)>; 433 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 434 interrupt-names = "irq_0"; 435 interrupt-parent = <&gic>; 436 clocks = <&ccm IMX_CCM_TPM3_CLK 0 0>; 437 prescaler = <1>; 438 status = "disabled"; 439 }; 440 441 tpm4: tpm@424f0000 { 442 compatible = "nxp,tpm-timer"; 443 reg = <0x424f0000 DT_SIZE_K(64)>; 444 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 445 interrupt-names = "irq_0"; 446 interrupt-parent = <&gic>; 447 clocks = <&ccm IMX_CCM_TPM4_CLK 0 0>; 448 prescaler = <1>; 449 status = "disabled"; 450 }; 451 452 tpm5: tpm@42500000 { 453 compatible = "nxp,tpm-timer"; 454 reg = <0x42500000 DT_SIZE_K(64)>; 455 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 456 interrupt-names = "irq_0"; 457 interrupt-parent = <&gic>; 458 clocks = <&ccm IMX_CCM_TPM5_CLK 0 0>; 459 prescaler = <1>; 460 status = "disabled"; 461 }; 462 463 tpm6: tpm@42510000 { 464 compatible = "nxp,tpm-timer"; 465 reg = <0x42510000 DT_SIZE_K(64)>; 466 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 467 interrupt-names = "irq_0"; 468 interrupt-parent = <&gic>; 469 clocks = <&ccm IMX_CCM_TPM6_CLK 0 0>; 470 prescaler = <1>; 471 status = "disabled"; 472 }; 473 474}; 475 476&gpio1{ 477 pinmux = <&iomuxc1_i2c1_scl_gpio_io_gpio1_io00>, 478 <&iomuxc1_i2c1_sda_gpio_io_gpio1_io01>, 479 <&iomuxc1_i2c2_scl_gpio_io_gpio1_io02>, 480 <&iomuxc1_i2c2_sda_gpio_io_gpio1_io03>, 481 <&iomuxc1_uart1_rxd_gpio_io_gpio1_io04>, 482 <&iomuxc1_uart1_txd_gpio_io_gpio1_io05>, 483 <&iomuxc1_uart2_rxd_gpio_io_gpio1_io06>, 484 <&iomuxc1_uart2_txd_gpio_io_gpio1_io07>, 485 <&iomuxc1_pdm_clk_gpio_io_gpio1_io08>, 486 <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09>, 487 <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, 488 <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, 489 <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, 490 <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, 491 <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, 492 <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; 493}; 494 495&gpio2{ 496 pinmux = <&iomuxc1_gpio_io00_gpio_io_gpio2_io00>, 497 <&iomuxc1_gpio_io01_gpio_io_gpio2_io01>, 498 <&iomuxc1_gpio_io02_gpio_io_gpio2_io02>, 499 <&iomuxc1_gpio_io03_gpio_io_gpio2_io03>, 500 <&iomuxc1_gpio_io04_gpio_io_gpio2_io04>, 501 <&iomuxc1_gpio_io05_gpio_io_gpio2_io05>, 502 <&iomuxc1_gpio_io06_gpio_io_gpio2_io06>, 503 <&iomuxc1_gpio_io07_gpio_io_gpio2_io07>, 504 <&iomuxc1_gpio_io08_gpio_io_gpio2_io08>, 505 <&iomuxc1_gpio_io09_gpio_io_gpio2_io09>, 506 <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, 507 <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, 508 <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, 509 <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, 510 <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, 511 <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, 512 <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, 513 <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, 514 <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, 515 <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, 516 <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, 517 <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, 518 <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, 519 <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, 520 <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, 521 <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, 522 <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, 523 <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, 524 <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, 525 <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; 526}; 527 528&gpio3{ 529 pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, 530 <&iomuxc1_sd2_clk_gpio_io_gpio3_io01>, 531 <&iomuxc1_sd2_cmd_gpio_io_gpio3_io02>, 532 <&iomuxc1_sd2_data0_gpio_io_gpio3_io03>, 533 <&iomuxc1_sd2_data1_gpio_io_gpio3_io04>, 534 <&iomuxc1_sd2_data2_gpio_io_gpio3_io05>, 535 <&iomuxc1_sd2_data3_gpio_io_gpio3_io06>, 536 <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>, 537 <&iomuxc1_sd1_clk_gpio_io_gpio3_io08>, 538 <&iomuxc1_sd1_cmd_gpio_io_gpio3_io09>, 539 <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, 540 <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, 541 <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, 542 <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, 543 <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, 544 <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, 545 <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, 546 <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, 547 <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, 548 <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, 549 <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, 550 <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, 551 <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, 552 <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, 553 <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, 554 <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, 555 <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, 556 <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, 557 <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, 558 <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, 559 <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, 560 <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; 561}; 562 563&gpio4{ 564 pinmux = <&iomuxc1_enet1_mdc_gpio_io_gpio4_io00>, 565 <&iomuxc1_enet1_mdio_gpio_io_gpio4_io01>, 566 <&iomuxc1_enet1_td3_gpio_io_gpio4_io02>, 567 <&iomuxc1_enet1_td2_gpio_io_gpio4_io03>, 568 <&iomuxc1_enet1_td1_gpio_io_gpio4_io04>, 569 <&iomuxc1_enet1_td0_gpio_io_gpio4_io05>, 570 <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06>, 571 <&iomuxc1_enet1_txc_gpio_io_gpio4_io07>, 572 <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08>, 573 <&iomuxc1_enet1_rxc_gpio_io_gpio4_io09>, 574 <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, 575 <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, 576 <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, 577 <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, 578 <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, 579 <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, 580 <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, 581 <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, 582 <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, 583 <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, 584 <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, 585 <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, 586 <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, 587 <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, 588 <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, 589 <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, 590 <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, 591 <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, 592 <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, 593 <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; 594}; 595
