Lines Matching +full:0 +full:xc0000
21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0x100>;
57 reg = <0x48000000 0x10000>, /* GIC Dist */
58 <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */
66 reg = <0x443c0000 DT_SIZE_K(64)>;
76 reg = <0x44480000 DT_SIZE_K(64)>;
81 reg = <0x44450000 DT_SIZE_K(64)>;
87 reg = <0x47400000 DT_SIZE_K(64)>;
97 reg = <0x43810000 DT_SIZE_K(64)>;
107 reg = <0x43820000 DT_SIZE_K(64)>;
117 reg = <0x43830000 DT_SIZE_K(64)>;
127 reg = <0x44380000 DT_SIZE_K(64)>;
131 clocks = <&ccm IMX_CCM_LPUART1_CLK 0x6c 24>;
137 reg = <0x44390000 DT_SIZE_K(64)>;
141 clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>;
149 #size-cells = <0>;
150 reg = <0x44340000 0x4000>;
153 clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>;
161 #size-cells = <0>;
162 reg = <0x44350000 0x4000>;
165 clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>;
173 #size-cells = <0>;
174 reg = <0x42530000 0x4000>;
177 clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>;
185 #size-cells = <0>;
186 reg = <0x42540000 0x4000>;
189 clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>;
197 #size-cells = <0>;
198 reg = <0x426b0000 0x4000>;
201 clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>;
209 #size-cells = <0>;
210 reg = <0x426c0000 0x4000>;
213 clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>;
221 #size-cells = <0>;
222 reg = <0x426d0000 0x4000>;
225 clocks = <&ccm IMX_CCM_LPI2C7_CLK 0x80 24>;
233 #size-cells = <0>;
234 reg = <0x426e0000 0x4000>;
237 clocks = <&ccm IMX_CCM_LPI2C8_CLK 0x80 24>;
243 reg = <0x44360000 0x4000>;
247 clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>;
249 #size-cells = <0>;
254 reg = <0x44370000 0x4000>;
258 clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>;
260 #size-cells = <0>;
265 reg = <0x42550000 0x4000>;
269 clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>;
271 #size-cells = <0>;
276 reg = <0x42560000 0x4000>;
280 clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>;
282 #size-cells = <0>;
287 reg = <0x426f0000 0x4000>;
291 clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>;
293 #size-cells = <0>;
298 reg = <0x42700000 0x4000>;
302 clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>;
304 #size-cells = <0>;
309 reg = <0x42710000 0x4000>;
313 clocks = <&ccm IMX_CCM_LPSPI7_CLK 0x6c 0>;
315 #size-cells = <0>;
320 reg = <0x42720000 0x4000>;
324 clocks = <&ccm IMX_CCM_LPSPI8_CLK 0x6c 2>;
326 #size-cells = <0>;
331 reg = <0x443a0000 DT_SIZE_K(64)>;
336 clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
337 clk-source = <0>;
343 reg = <0x425b0000 DT_SIZE_K(64)>;
348 clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
349 clk-source = <0>;
355 reg = <0x42000000 (DT_SIZE_K(64) * 32)>;
356 valid-channels = <0>, <1>;
366 reg = <0x42660000 DT_SIZE_K(64)>;
368 clocks = <&ccm IMX_CCM_SAI3_CLK 0x0 0x0>;
373 dmas = <&edma4 0 60>, <&edma4 1 61>;
380 reg = <0x42890000 DT_SIZE_K(64)>;
381 clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
396 #size-cells = <0>;
403 clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
410 reg = <0x44310000 DT_SIZE_K(64)>;
414 clocks = <&ccm IMX_CCM_TPM1_CLK 0 0>;
421 reg = <0x44320000 DT_SIZE_K(64)>;
425 clocks = <&ccm IMX_CCM_TPM2_CLK 0 0>;
432 reg = <0x424e0000 DT_SIZE_K(64)>;
436 clocks = <&ccm IMX_CCM_TPM3_CLK 0 0>;
443 reg = <0x424f0000 DT_SIZE_K(64)>;
447 clocks = <&ccm IMX_CCM_TPM4_CLK 0 0>;
454 reg = <0x42500000 DT_SIZE_K(64)>;
458 clocks = <&ccm IMX_CCM_TPM5_CLK 0 0>;
465 reg = <0x42510000 DT_SIZE_K(64)>;
469 clocks = <&ccm IMX_CCM_TPM6_CLK 0 0>;