Lines Matching +full:0 +full:xc0000
25 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
68 reg = <0x38800000 0x10000>, /* GIC Dist */
69 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
77 reg = <0x30200000 DT_SIZE_K(64)>;
91 reg = <0x30210000 DT_SIZE_K(64)>;
105 reg = <0x30220000 DT_SIZE_K(64)>;
119 reg = <0x30230000 DT_SIZE_K(64)>;
128 gpio-reserved-ranges = <0 21>;
134 reg = <0x30240000 DT_SIZE_K(64)>;
148 reg = <0x302d0000 DT_SIZE_K(64)>;
153 clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>;
159 reg = <0x302e0000 DT_SIZE_K(64)>;
164 clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>;
170 reg = <0x30330000 DT_SIZE_K(64)>;
180 reg = <0x30360000 DT_SIZE_K(64)>;
185 reg = <0x30380000 DT_SIZE_K(64)>;
191 reg = <0x30890000 DT_SIZE_K(64)>;
195 clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
203 reg = <0x30a60000 DT_SIZE_K(64)>;
207 clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
215 reg = <0x303d0000 DT_SIZE_K(64)>;
220 reg = <0x30be0000 DT_SIZE_K(64)>;
221 clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
237 #size-cells = <0>;
244 clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
348 pinmux = <0x0 0 0x0 0 0x0>;