Lines Matching +full:0 +full:xc0000
25 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
68 reg = <0x38800000 0x10000>, /* GIC Dist */
69 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
77 reg = <0x30200000 DT_SIZE_K(64)>;
91 reg = <0x30210000 DT_SIZE_K(64)>;
105 reg = <0x30220000 DT_SIZE_K(64)>;
119 reg = <0x30230000 DT_SIZE_K(64)>;
133 reg = <0x30240000 DT_SIZE_K(64)>;
147 reg = <0x302d0000 DT_SIZE_K(64)>;
152 clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>;
158 reg = <0x302e0000 DT_SIZE_K(64)>;
163 clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>;
169 reg = <0x30330000 DT_SIZE_K(64)>;
179 reg = <0x30360000 DT_SIZE_K(64)>;
184 reg = <0x30380000 DT_SIZE_K(64)>;
190 reg = <0x30890000 DT_SIZE_K(64)>;
194 clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
202 reg = <0x30a60000 DT_SIZE_K(64)>;
206 clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
214 reg = <0x303d0000 DT_SIZE_K(64)>;
219 reg = <0x30be0000 DT_SIZE_K(64)>;
220 clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
236 #size-cells = <0>;
243 clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;