Lines Matching +full:0 +full:xc0000
20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
62 reg = <0x38800000 0x10000>, /* GIC Dist */
63 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
72 reg = <0x30360000 DT_SIZE_K(64)>;
77 reg = <0x30380000 DT_SIZE_K(64)>;
83 reg = <0x30200000 DT_SIZE_K(64)>;
96 reg = <0x30210000 DT_SIZE_K(64)>;
109 reg = <0x30220000 DT_SIZE_K(64)>;
122 reg = <0x30230000 DT_SIZE_K(64)>;
135 reg = <0x30240000 DT_SIZE_K(64)>;
148 reg = <0x302d0000 DT_SIZE_K(64)>;
153 clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>;
159 reg = <0x302e0000 DT_SIZE_K(64)>;
164 clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>;
170 reg = <0x30890000 DT_SIZE_K(64)>;
174 clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
182 reg = <0x30a60000 DT_SIZE_K(64)>;
186 clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
194 reg = <0x30be0000 DT_SIZE_K(64)>;
195 clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
211 #size-cells = <0>;
218 clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
225 reg = <0x30330000 DT_SIZE_K(64)>;
235 reg = <0x303d0000 DT_SIZE_K(64)>;