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/Zephyr-latest/tests/drivers/flash/common/boards/
Dmax32690evkit_max32690_m4.overlay13 code_partition: partition@0 {
14 reg = <0x0 DT_SIZE_M(2)>;
20 reg = <0x200000 DT_SIZE_K(1)>;
Dmax32690fthr_max32690_m4.overlay13 code_partition: partition@0 {
14 reg = <0x0 DT_SIZE_M(2)>;
20 reg = <0x200000 DT_SIZE_K(1)>;
Dmax78002evkit_max78002_m4.overlay13 code_partition: partition@0 {
14 reg = <0x0 DT_SIZE_M(2)>;
20 reg = <0x200000 DT_SIZE_K(512)>;
/Zephyr-latest/dts/common/broadcom/
Dviper-common.dtsi11 reg = <0x00400000 0x80000>;
16 reg = <0x40020000 0x400>;
24 reg = <0x48100000 0x400>;
32 reg = <0x48300000 0x2000>,
33 <0x482f005c 0x20>;
36 microcode = <0x63b00000 0x1000>;
48 reg = <0x0 0x4e100000 0x0 0x2100>,
49 <0x0 0x50000000 0x0 0x8000000>,
50 <0x4 0x0 0x0 0x8000000>;
53 dmas = <&pl330 0>, <&pl330 1>;
[all …]
/Zephyr-latest/boards/arm/v2m_musca_b1/
Dv2m_musca_b1.dts32 gpios = <&gpio 2 0>;
36 gpios = <&gpio 3 0>;
40 gpios = <&gpio 4 0>;
47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
58 reg = <0xe000ed90 0x40>;
65 reg = <0x1a000000 0x200000>;
70 reg = <0x30000000 0x80000>;
76 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dnordic,owned-partitions.yaml22 reg = <0xe000000 0x200000>;
32 label = "image-0";
33 reg = <0xc0000 0x40000>;
45 reg = <0x100000 0x50000>;
49 reg = <0x150000 0x6000>;
56 - 0x0E0C0000--0x0E100000, with read & execute permissions, containing the
57 partition labeled "image-0".
58 - 0x0E100000--0x0E156000, with read & write permissions, containing the
/Zephyr-latest/boards/arm/v2m_musca_s1/
Dv2m_musca_s1.dts32 gpios = <&gpio 2 0>;
36 gpios = <&gpio 3 0>;
40 gpios = <&gpio 4 0>;
47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
58 reg = <0xe000ed90 0x40>;
65 reg = <0x1a000000 0x200000>;
70 reg = <0x10200000 0x2000000>;
75 reg = <0x30000000 0x80000>;
[all …]
/Zephyr-latest/dts/riscv/sensry/
Dganymed-sy1xx.dtsi8 #size-cells = <0>;
12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 reg = <0>;
27 reg = <0x1c010200 0x5fe00>;
35 reg = <0x1c070000 0x200000>;
41 #size-cells = <0>;
45 reg = <0x1000>;
52 reg = <0x1a10b040>;
54 interrupts = <10 0>;
[all …]
/Zephyr-latest/dts/arm64/broadcom/
Dbcm2711.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
43 reg = <0x200000 0x80000>;
48 reg = <0xff841000 0x1000>,
49 <0xff842000 0x2000>;
57 reg = <0xfe200000 0xf4>;
59 #size-cells = <0>;
61 /* GPIO 0 ~ 27 */
62 gpio0: gpio@0 {
[all …]
Dbcm2712.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
43 reg = <0x0 0x200000 0x80000>;
48 reg = <0x10 0x7fff9000 0x1000>,
49 <0x10 0x7fffa000 0x2000>;
57 reg = <0x10 0x7d517c00 0x40>;
60 #size-cells = <0>;
61 gio_aon: gpio@0 {
63 reg = <0>;
[all …]
/Zephyr-latest/boards/adafruit/feather_stm32f405/
Dadafruit_feather_stm32f405.dts64 pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
71 pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
80 pinctrl-0 = <&spi1_nss_pa15 &spi1_sck_pb3
85 gd25q16: gd25q16c@0 {
87 reg = <0>;
89 size = <0x200000>;
98 pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
104 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
110 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
/Zephyr-latest/dts/arm64/fvp/
Dfvp-aemv8r.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
56 #clock-cells = <0>;
64 reg = <0xaf000000 0x10000>,
65 <0xaf100000 0x200000>;
73 reg = <0x9c090000 0x10000>;
82 reg = <0x9c0a0000 0x10000>;
91 reg = <0x9c0b0000 0x10000>;
100 reg = <0x9c0c0000 0x10000>;
[all …]
/Zephyr-latest/tests/bluetooth/controller/common/include/
Dhelper_features.h13 #define FEAT_ENCODED 0x01
15 #define FEAT_ENCODED 0x00
19 #define FEAT_PARAM_REQ 0x02
21 #define FEAT_PARAM_REQ 0x00
25 #define FEAT_EXT_REJ 0x04
27 #define FEAT_EXT_REJ 0x00
31 #define FEAT_PERIPHERAL_FREQ 0x08
33 #define FEAT_PERIPHERAL_FREQ 0x00
37 #define FEAT_PING 0x10
39 #define FEAT_PING 0x00
[all …]
/Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/
Dfvp_base_revc_2xaemv8a.dts33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
44 reg = <0x100>;
50 reg = <0x200>;
56 reg = <0x300>;
76 #clock-cells = <0>;
84 reg = <0x2f000000 0x10000>, // GICD
85 <0x2f100000 0x200000>; // GICR
94 reg = <0x2f020000 0x20000>;
[all …]
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex.dtsi16 #size-cells= <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
27 reg = <0x1>;
33 reg = <0x2>;
39 reg = <0x3>;
45 reg = <0xfffc1000 0x1000>,
46 <0xfffc2000 0x2000>;
67 reg = <0xffd12000 0x1000>;
72 reg = <0xffd10000 0x1000>;
[all …]
/Zephyr-latest/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/
Dmps2_an521-common.dtsi10 #clock-cells = <0>;
13 timer0: timer@0 {
15 reg = <0x0 0x1000>;
21 reg = <0x1000 0x1000>;
27 reg = <0x2000 0x1000>;
33 reg = <0x3000 0x1000>;
39 reg = <0x4000 0x1000>;
45 reg = <0x100000 0x1000>;
53 reg = <0x101000 0x1000>;
61 reg = <0x102000 0x1000>;
[all …]
/Zephyr-latest/boards/arm/mps2/
Dmps2_an521-common.dtsi10 #clock-cells = <0>;
13 timer0: timer@0 {
15 reg = <0x0 0x1000>;
21 reg = <0x1000 0x1000>;
27 reg = <0x2000 0x1000>;
33 reg = <0x3000 0x1000>;
39 reg = <0x4000 0x1000>;
45 reg = <0x100000 0x1000>;
53 reg = <0x101000 0x1000>;
61 reg = <0x102000 0x1000>;
[all …]
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu740.dtsi18 #clock-cells = <0>;
24 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
43 #address-cells = <0>;
52 reg = <0x1>;
57 #address-cells = <0>;
66 reg = <0x2>;
71 #address-cells = <0>;
[all …]
/Zephyr-latest/soc/altr/qemu_nios2/include/
Dsystem.h53 #define ALT_CPU_BIG_ENDIAN 0
54 #define ALT_CPU_BREAK_ADDR 0x00200820
58 #define ALT_CPU_CPU_ID_VALUE 0x00000000
60 #define ALT_CPU_DATA_ADDR_WIDTH 0x17
61 #define ALT_CPU_DCACHE_LINE_SIZE 0
62 #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
63 #define ALT_CPU_DCACHE_SIZE 0
64 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
65 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
66 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
[all …]
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dlinker.ld32 #define ROM_BASE 0x1C010100
33 #define ROM_SIZE 0x5Fa00
36 #define RAM_BASE 0x1C070000
37 #define RAM_SIZE 0x200000
41 L2_START (rx) : ORIGIN = 0x1c010000, LENGTH = 0x00000080
42 L2_VALIDITY (rx) : ORIGIN = 0x1c010080, LENGTH = 0x00000080
47 L2_PRIV_CH0 : ORIGIN = 0x1c004100, LENGTH = 0x2000 /* uDMA access */
53 IDT_LIST : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
61 .pre_start MAX(0x1c010000,ALIGN(0x80)) :
66 .validity_marker MAX(0x1c010080,ALIGN(0x80)) :
[all …]
/Zephyr-latest/dts/riscv/starfive/
Djh7110-visionfive-v2.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
25 reg = <0>;
50 reg = <0x1>;
75 reg = <0x2>;
100 reg = <0x3>;
125 reg = <0x4>;
138 reg = <0x0 0x8000000 0x0 0x200000>;
155 reg = <0x0 0x2000000 0x0 0x10000>;
167 reg = <0x0 0x2010000 0x0 0x4000>;
[all …]
/Zephyr-latest/boards/beagle/beagleconnect_freedom/
Dbeagleconnect_freedom.dts53 * Off 0 0
54 * Sub-1 GHz 0 1 // DIO30 mux to IOC_PORT_RFC_GPO0 for auto
55 * 20 dBm TX 1 0 // DIO29 mux to IOC_PORT_RFC_GPO3 for auto
61 pinctrl-0 = <&board_ant_tx_pa_off &board_ant_subg_off>;
78 #size-cells = <0>;
85 reg = <0x44>;
91 reg = <0x41>;
103 boot_partition: partition@0 {
105 reg = <0x00000000 0x00020000>;
110 label = "image-0";
[all …]
/Zephyr-latest/include/zephyr/arch/nios2/
Dnios2.h69 __asm__("mov %0, et" : "=r" (et)); in _nios2_read_et()
82 __asm__("mov %0, sp" : "=r" (sp)); in _nios2_read_sp()
104 __asm__ volatile ("flushda (%0)" :: "r" (addr)); in _nios2_dcache_addr_flush()
109 __asm__ volatile ("flushd (%0)" :: "r" (offset)); in z_nios2_dcache_flush()
114 __asm__ volatile ("flushi %0" :: "r" (offset)); in z_nios2_icache_flush()
127 NIOS2_CR_STATUS = 0,
147 * we get errors "Control register number must be in range 0-31 for
201 #define NIOS2_STATUS_PIE_MSK (0x00000001)
202 #define NIOS2_STATUS_PIE_OFST (0)
203 #define NIOS2_STATUS_U_MSK (0x00000002)
[all …]
/Zephyr-latest/soc/altr/zephyr_nios2f/include/
Dsystem.h64 #define ALT_CPU_BIG_ENDIAN 0
65 #define ALT_CPU_BREAK_ADDR 0x00200820
69 #define ALT_CPU_CPU_ID_VALUE 0x00000000
71 #define ALT_CPU_DATA_ADDR_WIDTH 0x1c
72 #define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
76 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
77 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
78 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
83 #define ALT_CPU_HARDWARE_MULX_PRESENT 0
94 #define ALT_CPU_INST_ADDR_WIDTH 0x1c
[all …]
/Zephyr-latest/modules/nrf_wifi/bus/
Drpu_hw_if.c43 { 0x000000, 0x008FFF, 1 },
44 { 0x009000, 0x03FFFF, 2 },
45 { 0x040000, 0x07FFFF, 1 },
46 { 0x0C0000, 0x0F0FFF, 0 },
47 { 0x080000, 0x092000, 2 },
48 { 0x100000, 0x134000, 1 },
49 { 0x140000, 0x14C000, 1 },
50 { 0x180000, 0x190000, 1 },
51 { 0x200000, 0x261800, 1 },
52 { 0x280000, 0x2A4000, 1 },
[all …]

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