1/* Copyright (c) 2024 sensry.io */
2/* SPDX-License-Identifier: Apache-2.0 */
3
4/dts-v1/;
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <0>;
9
10	cpus {
11		#address-cells = <1>;
12		#size-cells = <0>;
13
14		cpu0: cpu@0 {
15			compatible = "sensry,sy1xx", "riscv";
16			reg = <0>;
17			riscv,isa = "rv32imc_zicsr";
18			status = "okay";
19		};
20
21	};
22
23	l2_ram_text: memory@1c010200 {
24		#address-cells = <1>;
25		#size-cells = <1>;
26		compatible = "mmio-sram";
27		reg = <0x1c010200 0x5fe00>;
28		status = "okay";
29	};
30
31	l2_ram_data: memory@1c070000 {
32		#address-cells = <1>;
33		#size-cells = <1>;
34		compatible = "mmio-sram";
35		reg = <0x1c070000 0x200000>;
36		status = "okay";
37	};
38
39	soc {
40		#address-cells = <1>;
41		#size-cells = <0>;
42
43		event0: interrupt-controller@1000 {
44			compatible = "sensry,sy1xx-event-unit";
45			reg = <0x1000>;
46			interrupt-controller;
47			#interrupt-cells = <1>;
48		};
49
50		systick: timer@1a10b040 {
51			compatible = "sensry,sy1xx-sys-timer";
52			reg = <0x1a10b040>;
53			interrupt-parent = <&event0>;
54			interrupts = <10 0>;
55			ticks_us = <1000>;
56		};
57
58		timer1: timer@1a10b044 {
59			compatible = "sensry,sy1xx-sys-timer";
60			reg = <0x1a10b044>;
61			interrupt-parent = <&event0>;
62			interrupts = <11 0>;
63			ticks_us = <1000>;
64		};
65
66		uart0: uart@1a102000 {
67			compatible = "sensry,sy1xx-uart";
68			reg = <0x1a102000>;
69			instance = <0>;
70			current-speed = <1000000>;
71			status = "okay";
72		};
73
74		uart1: uart@1a102080 {
75			compatible = "sensry,sy1xx-uart";
76			reg = <0x1a102080>;
77			instance = <1>;
78			current-speed = <1000000>;
79			status = "okay";
80		};
81
82		uart2: uart@1a102100 {
83			compatible = "sensry,sy1xx-uart";
84			reg = <0x1a102100>;
85			instance = <2>;
86			current-speed = <1000000>;
87			status = "okay";
88		};
89
90	};
91};
92