43 	{ 0x000000, 0x008FFF, 1 },
44 	{ 0x009000, 0x03FFFF, 2 },
45 	{ 0x040000, 0x07FFFF, 1 },
46 	{ 0x0C0000, 0x0F0FFF, 0 },
47 	{ 0x080000, 0x092000, 2 },
48 	{ 0x100000, 0x134000, 1 },
49 	{ 0x140000, 0x14C000, 1 },
50 	{ 0x180000, 0x190000, 1 },
51 	{ 0x200000, 0x261800, 1 },
52 	{ 0x280000, 0x2A4000, 1 },
53 	{ 0x300000, 0x338000, 1 }
67 	if (((start_addr >= block_map[0]) && (start_addr <= block_map[1])) &&  in validate_addr_blk()
68 	    ((end_addr >= block_map[0]) && (end_addr <= block_map[1]))) {  in validate_addr_blk()
70 			*hl_flag = 0;  in validate_addr_blk()
73 		return 0;  in validate_addr_blk()
81 	int ret = 0, i;  in rpu_validate_addr()
89 	for (i = 0; i < NUM_MEM_BLOCKS; i++) {  in rpu_validate_addr()
106 	cfg->qspi_slave_latency = (*hl_flag) ? rpu_7002_memmap[selected_blk][2] : 0;  in rpu_validate_addr()
108 	return 0;  in rpu_validate_addr()
201 	return 0;  in rpu_gpio_config()
239 		gpio_pin_set_dt(&bucken_spec, 0);  in rpu_pwron()
263 	ret = gpio_pin_set_dt(&bucken_spec, 0); /* BUCKEN = 0 */  in rpu_pwroff()
269 	ret = gpio_pin_set_dt(&iovdd_ctrl_spec, 0); /* IOVDD CNTRL = 0 */  in rpu_pwroff()
324 	if (ret < 0) {  in rpu_wakeup()
330 	if (ret < 0) {  in rpu_wakeup()
335 	return 0;  in rpu_wakeup()
376 	LOG_DBG("Written 0x%x to WRSR2", data);  in rpu_wrsr2()
401 	uint32_t rpu_clks = 0x100;  in rpu_clks_on()
403 	qdev->write(0x048C20, &rpu_clks, 4);  in rpu_clks_on()
405 	return 0;  in rpu_clks_on()
408 #define RPU_EXP_SIG 0x42000020
416 	ret = rpu_read(0x0005C, &rpu_test, 4);  in rpu_validate_comms()
423 		LOG_ERR("Error: RPU comms test: sig failed: expected 0x%x, got 0x%x\n",  in rpu_validate_comms()
430 	return 0;  in rpu_validate_comms()
460 	return 0;  in rpu_init()
496 	return 0;  in rpu_enable()