1/*
2 * Copyright (c) 2019-2020 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <arm/armv8-m.dtsi>
10
11/ {
12	compatible = "arm,v2m-musca";
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	aliases {
17		led0 = &red_led;
18		led1 = &green_led;
19		led2 = &blue_led;
20	};
21
22	chosen {
23		zephyr,console = &uart1;
24		zephyr,sram = &sram0;
25		zephyr,flash = &mram0;
26		zephyr,shell-uart = &uart1;
27	};
28
29	leds {
30		compatible = "gpio-leds";
31		red_led: led_0 {
32			gpios = <&gpio 2 0>;
33			label = "User LED1";
34		};
35		green_led: led_1 {
36			gpios = <&gpio 3 0>;
37			label = "User LED2";
38		};
39		blue_led: led_2 {
40			gpios = <&gpio 4 0>;
41			label = "User LED3";
42		};
43	};
44
45	cpus {
46		#address-cells = <1>;
47		#size-cells = <0>;
48
49		cpu@0 {
50			device_type = "cpu";
51			compatible = "arm,cortex-m33";
52			reg = <0>;
53			#address-cells = <1>;
54			#size-cells = <1>;
55
56			mpu: mpu@e000ed90 {
57				compatible = "arm,armv8m-mpu";
58				reg = <0xe000ed90 0x40>;
59			};
60		};
61	};
62
63	mram0: mram@1a000000 {
64		/* Internal code eMRAM */
65		reg = <0x1a000000 0x200000>;
66	};
67
68	flash0: flash@10200000 {
69		/* External QSPI flash */
70		reg = <0x10200000 0x2000000>;
71	};
72
73	sram0: memory@30000000 {
74		compatible = "mmio-sram";
75		reg = <0x30000000 0x80000>;
76	};
77
78	sysclk: system-clock {
79		compatible = "fixed-clock";
80		clock-frequency = <50000000>;
81		#clock-cells = <0>;
82	};
83
84	scc@5010b000 {
85		compatible = "arm,scc";
86		reg = <0x5010b000 0x1000>;
87	};
88
89	soc {
90		peripheral@50000000 {
91			#address-cells = <1>;
92			#size-cells = <1>;
93			ranges = <0x0 0x50000000 0x10000000>;
94
95			#include "v2m_musca_s1-common.dtsi"
96		};
97	};
98
99};
100
101&nvic {
102	arm,num-irq-priority-bits = <3>;
103};
104