| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/ |
| D | xg22-pinctrl.h | 16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1)
21 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 15, 1, 0, 1)
25 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1)
28 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1)
31 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1)
34 #define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2)
36 #define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1)
37 #define SILABS_DBUS_EUART0_RX(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 3)
39 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 38, 1, 0, 1)
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| D | xg27-pinctrl.h | 16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
23 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
28 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
30 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
34 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1)
37 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1)
40 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
43 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
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| D | xg24-pinctrl.h | 16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2)
39 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1)
43 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 42, 1, 0, 1)
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| D | xg21-pinctrl.h | 16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1)
29 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1)
32 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 26, 1, 0, 1)
35 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 30, 1, 0, 1)
38 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 34, 1, 0, 1)
42 #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 34, 0, 0, 4)
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| D | xg23-pinctrl.h | 16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
39 #define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1)
44 #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2)
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| /Zephyr-latest/arch/arm64/core/ |
| D | early_mem_funcs.S | 26 tst x0, #0x7
30 cmp x2, #8
34 and x8, x1, #0xff
35 mov x9, #0x0101010101010101
39 sub x2, x2, #8
40 cmp x2, #7
45 cbz x2, 4f
48 subs x2, x2, #1
60 tst x8, #0x7
64 cmp x2, #8
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| D | switch.S | 57 lsr x2, x4, #TPIDRROEL0_EXC_SHIFT
63 orr x4, x4, x2, lsl #TPIDRROEL0_EXC_SHIFT
84 ldr x2, [x0, #_thread_offset_to_tls]
90 msr tpidr_el0, x2
114 ldr x2, [x0, #_thread_offset_to_stack_limit]
115 str x2, [x4, #_cpu_offset_to_current_stack_limit]
148 cmp x1, #0x07 /*Access to SIMD or floating-point */
156 cmp x1, #0x15 /* 0x15 = SVC */
160 and x1, x0, #0xff
183 get_cpu x2
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| /Zephyr-latest/include/zephyr/dt-bindings/sensor/ |
| D | lsm6dsv16x.h | 10 #define LSM6DSV16X_DT_FS_2G 0
16 #define LSM6DSV16X_DT_FS_125DPS 0x0
17 #define LSM6DSV16X_DT_FS_250DPS 0x1
18 #define LSM6DSV16X_DT_FS_500DPS 0x2
19 #define LSM6DSV16X_DT_FS_1000DPS 0x3
20 #define LSM6DSV16X_DT_FS_2000DPS 0x4
21 #define LSM6DSV16X_DT_FS_4000DPS 0xc
24 #define LSM6DSV16X_DT_ODR_OFF 0x0
25 #define LSM6DSV16X_DT_ODR_AT_1Hz875 0x1
26 #define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
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| /Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/boards/ |
| D | native_posix.overlay | 17 reg = < 0xdeadbeef 0x10>;
18 #gpio-cells = < 0x2 >;
21 gpio-reserved-ranges = <0 4>, <5 3>, <9 5>, <11 2>,
29 reg = < 0xabcd1234 0x10>;
30 #gpio-cells = < 0x2 >;
33 gpio-reserved-ranges = <0 8>, <9 5>, <14 0>, <15 16>;
39 reg = < 0x1234 0x10 >;
40 #gpio-cells = < 0x2 >;
44 gpio-reserved-ranges = <0 0>, <3 2>, <10 1>;
50 reg = < 0x5678 0x10 >;
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_nxp_fs26.h | 13 #define FS26_M_FS (0x1 << 31)
16 #define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT)
19 /* Read/Write (reading = 0) */
20 #define FS26_RW (0x1 << 24)
26 #define FS26_DEV_STATUS_MASK (0xff << FS26_DEV_STATUS_SHIFT)
29 #define FS26_M_AVAL (0x1 << 31)
31 #define FS26_FS_EN (0x1 << 30)
33 #define FS26_FS_G (0x1 << 29)
35 #define FS26_COM_G (0x1 << 28)
37 #define FS26_WIO_G (0x1 << 27)
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | esp-pinctrl-common.h | 12 #define ESP32_PIN_NUM_SHIFT 0U
13 #define ESP32_PIN_NUM_MASK 0x3FU
20 #define ESP32_PIN_SIGI_MASK 0x1FFU
22 #define ESP32_PIN_SIGO_MASK 0x1FFU
36 #define ESP32_PIN_BIAS_SHIFT 0U
37 #define ESP32_PIN_BIAS_MASK 0x3U
39 #define ESP32_PIN_DRV_MASK 0x3U
41 #define ESP32_PIN_OUT_MASK 0x3U
43 #define ESP32_PIN_EN_DIR_MASK 0x3U
46 #define ESP32_NO_PULL 0x1
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| /Zephyr-latest/include/zephyr/posix/sys/ |
| D | mman.h | 13 #define PROT_NONE 0x0
14 #define PROT_READ 0x1
15 #define PROT_WRITE 0x2
16 #define PROT_EXEC 0x4
18 #define MAP_SHARED 0x1
19 #define MAP_PRIVATE 0x2
20 #define MAP_FIXED 0x4
23 #define MAP_ANONYMOUS 0x20
25 #define MS_SYNC 0x0
26 #define MS_ASYNC 0x1
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| /Zephyr-latest/dts/bindings/dma/ |
| D | st,stm32u5-dma.yaml | 12 Tx using channel 0 with request 7
15 dmas = <&gpdma1 0 7 0x10440>,
16 <&gpdma1 1 6 0x10480>;
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
22 the slot is a value between <0> .. (<dma-requests> - 1).
26 0x0: MEM to MEM
27 0x1: MEM to PERIPH
28 0x2: PERIPH to MEM
29 0x3: reserved for PERIPH to PERIPH
31 0x0: no address increment between transfers
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| D | gd,gd32-dma.yaml | 11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
21 - 0x0: no address increase between transfers
22 - 0x1: increase address between transfers
25 - 0x0: 8 bits
26 - 0x1: 16 bits
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| D | gd,gd32-dma-v1.yaml | 13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
23 - 0x0: no address increase between transfers
24 - 0x1: increase address between transfers
27 - 0x0: 8 bits
28 - 0x1: 16 bits
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| D | st,stm32-dma-v1.yaml | 12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
20 0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
21 0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
22 0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
23 0x3: reserved for PERIPH to PERIPH
25 0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
26 0x1: STM32_DMA_PERIPH_INC: increment address between transfers
28 0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
29 0x1: STM32_DMA_MEM_INC: increment address between transfers
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| D | st,stm32-dmamux.yaml | 11 1. channel: the mux channel from 0 to <dma-channels> - 1
16 0x0: MEM to MEM
17 0x1: MEM to PERIPH
18 0x2: PERIPH to MEM
19 0x3: reserved for PERIPH to PERIPH
21 0x0: no address increment between transfers
22 0x1: increment address between transfers
24 0x0: no address increment between transfers
25 0x1: increment address between transfers
27 0x0: Byte (8 bits)
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| D | st,stm32-bdma.yaml | 13 1. channel: the bdma stream from 0 to <bdma-requests>
18 0x0: MEM to MEM
19 0x1: MEM to PERIPH
20 0x2: PERIPH to MEM
21 0x3: reserved for PERIPH to PERIPH
23 0x0: no address increment between transfers
24 0x1: increment address between transfers
26 0x0: no address increment between transfers
27 0x1: increment address between transfers
29 0x0: Byte (8 bits)
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx-alts-map.dtsi | 12 /* SCFG DEVALT 0 */
14 alts = <&scfg 0x00 0x0 0>;
17 alts = <&scfg 0x00 0x3 1>;
21 alts = <&scfg 0x00 0x7 1>;
26 alts = <&scfg 0x01 0x0 0>;
29 alts = <&scfg 0x01 0x2 0>;
32 alts = <&scfg 0x01 0x3 0>;
35 alts = <&scfg 0x01 0x4 1>;
38 alts = <&scfg 0x01 0x5 0>;
41 alts = <&scfg 0x01 0x6 0>;
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| /Zephyr-latest/tests/drivers/stepper/drv8424/emul/boards/ |
| D | native_sim.overlay | 14 dir-gpios = <&gpio1 0 0>; /* D3 */
15 step-gpios = <&gpio1 1 0>; /* D4 */
16 sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
17 en-gpios = <&gpio2 1 0>; /* 5 */
18 m0-gpios = <&gpio3 0 0>;
19 m1-gpios = <&gpio3 1 0>;
23 #size-cells = <0>;
24 #stepper-motor-cells = <0>;
29 #gpio-cells = <0x2>;
36 #gpio-cells = <0x2>;
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| /Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/ |
| D | native_sim.overlay | 14 dir-gpios = <&gpio1 0 0>; /* D3 */
15 step-gpios = <&gpio1 1 0>; /* D4 */
16 sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
17 en-gpios = <&gpio2 1 0>; /* 5 */
18 m0-gpios = <&gpio3 0 0>;
19 m1-gpios = <&gpio3 1 0>;
23 #size-cells = <0>;
24 #stepper-motor-cells = <0>;
29 #gpio-cells = <0x2>;
36 #gpio-cells = <0x2>;
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| /Zephyr-latest/doc/services/pm/images/ |
| D | devr-async-ops.svg | 1 …0 0 757 592" width="757px" zoomAndPan="magnify"><defs/><g><rect fill="#FFFFFF" height="368.5969" s…
23 alt usage == 0
56 LineThickness 0
59 LineThickness 0
62 LineThickness 0
69 LineThickness 0
201 alt usage == 0
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| /Zephyr-latest/dts/arm/ |
| D | cortex_r8_virt.dtsi | 15 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
30 reg = < 0xc0000000 0x2000000 >;
32 sram0: memory@0 {
34 reg = < 0x0 0x4000000 >;
38 reg = < 0xff000000 0x4c >;
47 interrupts = < 0x0 0x24 0x2 0xa0 >,
48 < 0x0 0x25 0x2 0xa0 >,
49 < 0x0 0x26 0x2 0xa0 >;
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| /Zephyr-latest/include/zephyr/drivers/sensor/ |
| D | wsen_hids_2525020210002.h | 28 hids_2525020210002_precision_Low = 0x0,
29 hids_2525020210002_precision_Medium = 0x1,
30 hids_2525020210002_precision_High = 0x2
34 hids_2525020210002_heater_Off = 0x0,
35 hids_2525020210002_heater_On_200mW_1s = 0x1,
36 hids_2525020210002_heater_On_200mW_100ms = 0x2,
37 hids_2525020210002_heater_On_110mW_1s = 0x3,
38 hids_2525020210002_heater_On_110mW_100ms = 0x4,
39 hids_2525020210002_heater_On_20mW_1s = 0x5,
40 hids_2525020210002_heater_On_20mW_100ms = 0x6,
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,stm32-qdec.yaml | 13 pinctrl-0:
24 0x1: Encoder mode 1 (Default)
25 0x2: Encoder mode 2
26 0x3: Encoder mode 3
28 0x10002: Encoder mode: Clock plus direction, x2 mode
29 0x10003: Encoder mode: Clock plus direction, x1 mode
30 0x10004: Encoder mode: Directional Clock, x2 mode
31 0x10005: Encoder mode: Directional Clock, x1 mode
32 0x10006: Quadrature encoder mode: x1 mode, counting on tim_ti1fp1
33 0x10007: Quadrature encoder mode: x1 mode, counting on tim_ti2fp2
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