Lines Matching +full:0 +full:x2
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
21 - 0x0: no address increase between transfers
22 - 0x1: increase address between transfers
25 - 0x0: 8 bits
26 - 0x1: 16 bits
27 - 0x2: 32 bits
28 - 0x3: reserved
31 - 0x0: 8 bits
32 - 0x1: 16 bits
33 - 0x2: 32 bits
34 - 0x3: reserved
37 - 0x0: offset size is linked to the peripheral bus width
38 - 0x1: offset size is fixed to 4 (32-bit alignment)
41 - 0x0: low
42 - 0x1: medium
43 - 0x2: high
44 - 0x3: very high
50 pinctrl-0 = <&spi0_default>;
54 dmas = <&dma0 3 0>, <&dma0 5 GD32_DMA_PRIORITY_HIGH>;