Lines Matching +full:0 +full:x2

16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
21 #define SILABS_DBUS_CMU_CLKIN0(port, pin)  SILABS_DBUS(port, pin, 7, 0, 0, 1)
23 #define SILABS_DBUS_EUSART0_CS(port, pin)   SILABS_DBUS(port, pin, 19, 1, 0, 1)
28 #define SILABS_DBUS_EUSART0_CTS(port, pin)  SILABS_DBUS(port, pin, 19, 0, 0, 2)
30 #define SILABS_DBUS_PTI_DCLK(port, pin)   SILABS_DBUS(port, pin, 27, 1, 0, 1)
34 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1)
37 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1)
40 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
43 #define SILABS_DBUS_MODEM_ANT0(port, pin)        SILABS_DBUS(port, pin, 44, 1, 0, 1)
58 #define SILABS_DBUS_MODEM_DIN(port, pin)         SILABS_DBUS(port, pin, 44, 0, 0, 15)
60 #define SILABS_DBUS_PDM_CLK(port, pin)  SILABS_DBUS(port, pin, 62, 1, 0, 1)
61 #define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 62, 0, 0, 2)
62 #define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 62, 0, 0, 3)
64 #define SILABS_DBUS_PRS0_ASYNCH0(port, pin)  SILABS_DBUS(port, pin, 67, 1, 0, 1)
81 #define SILABS_DBUS_TIMER0_CC0(port, pin)   SILABS_DBUS(port, pin, 85, 1, 0, 1)
88 #define SILABS_DBUS_TIMER1_CC0(port, pin)   SILABS_DBUS(port, pin, 93, 1, 0, 1)
95 #define SILABS_DBUS_TIMER2_CC0(port, pin)   SILABS_DBUS(port, pin, 101, 1, 0, 1)
102 #define SILABS_DBUS_TIMER3_CC0(port, pin)   SILABS_DBUS(port, pin, 109, 1, 0, 1)
109 #define SILABS_DBUS_TIMER4_CC0(port, pin)   SILABS_DBUS(port, pin, 117, 1, 0, 1)
116 #define SILABS_DBUS_USART0_CS(port, pin)  SILABS_DBUS(port, pin, 125, 1, 0, 1)
121 #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 125, 0, 0, 2)
123 #define SILABS_DBUS_USART1_CS(port, pin)  SILABS_DBUS(port, pin, 133, 1, 0, 1)
128 #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2)
130 #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
131 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
132 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
133 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
134 #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
135 #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
136 #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
137 #define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
138 #define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
139 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
140 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
141 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
142 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
143 #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
144 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
145 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
146 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
147 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
148 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
149 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
150 #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
151 #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
152 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
153 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
154 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
155 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
157 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
158 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
159 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
160 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
161 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
162 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
163 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
164 #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
165 #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
166 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
167 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
168 #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
169 #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
170 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
171 #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
172 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
173 #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
174 #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
175 #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
176 #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
177 #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
178 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
179 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
180 #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
181 #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
182 #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
183 #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
184 #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
185 #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
186 #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
187 #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
188 #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
189 #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
190 #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
191 #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
192 #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
193 #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
194 #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
195 #define CMU_CLKIN0_PC0  SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
196 #define CMU_CLKIN0_PC1  SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
197 #define CMU_CLKIN0_PC2  SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
198 #define CMU_CLKIN0_PC3  SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
199 #define CMU_CLKIN0_PC4  SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
200 #define CMU_CLKIN0_PC5  SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
201 #define CMU_CLKIN0_PC6  SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
202 #define CMU_CLKIN0_PC7  SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
203 #define CMU_CLKIN0_PD0  SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
204 #define CMU_CLKIN0_PD1  SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
205 #define CMU_CLKIN0_PD2  SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
206 #define CMU_CLKIN0_PD3  SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
208 #define EUSART0_CS_PA0   SILABS_DBUS_EUSART0_CS(0x0, 0x0)
209 #define EUSART0_CS_PA1   SILABS_DBUS_EUSART0_CS(0x0, 0x1)
210 #define EUSART0_CS_PA2   SILABS_DBUS_EUSART0_CS(0x0, 0x2)
211 #define EUSART0_CS_PA3   SILABS_DBUS_EUSART0_CS(0x0, 0x3)
212 #define EUSART0_CS_PA4   SILABS_DBUS_EUSART0_CS(0x0, 0x4)
213 #define EUSART0_CS_PA5   SILABS_DBUS_EUSART0_CS(0x0, 0x5)
214 #define EUSART0_CS_PA6   SILABS_DBUS_EUSART0_CS(0x0, 0x6)
215 #define EUSART0_CS_PA7   SILABS_DBUS_EUSART0_CS(0x0, 0x7)
216 #define EUSART0_CS_PA8   SILABS_DBUS_EUSART0_CS(0x0, 0x8)
217 #define EUSART0_CS_PB0   SILABS_DBUS_EUSART0_CS(0x1, 0x0)
218 #define EUSART0_CS_PB1   SILABS_DBUS_EUSART0_CS(0x1, 0x1)
219 #define EUSART0_CS_PB2   SILABS_DBUS_EUSART0_CS(0x1, 0x2)
220 #define EUSART0_CS_PB3   SILABS_DBUS_EUSART0_CS(0x1, 0x3)
221 #define EUSART0_CS_PB4   SILABS_DBUS_EUSART0_CS(0x1, 0x4)
222 #define EUSART0_CS_PC0   SILABS_DBUS_EUSART0_CS(0x2, 0x0)
223 #define EUSART0_CS_PC1   SILABS_DBUS_EUSART0_CS(0x2, 0x1)
224 #define EUSART0_CS_PC2   SILABS_DBUS_EUSART0_CS(0x2, 0x2)
225 #define EUSART0_CS_PC3   SILABS_DBUS_EUSART0_CS(0x2, 0x3)
226 #define EUSART0_CS_PC4   SILABS_DBUS_EUSART0_CS(0x2, 0x4)
227 #define EUSART0_CS_PC5   SILABS_DBUS_EUSART0_CS(0x2, 0x5)
228 #define EUSART0_CS_PC6   SILABS_DBUS_EUSART0_CS(0x2, 0x6)
229 #define EUSART0_CS_PC7   SILABS_DBUS_EUSART0_CS(0x2, 0x7)
230 #define EUSART0_CS_PD0   SILABS_DBUS_EUSART0_CS(0x3, 0x0)
231 #define EUSART0_CS_PD1   SILABS_DBUS_EUSART0_CS(0x3, 0x1)
232 #define EUSART0_CS_PD2   SILABS_DBUS_EUSART0_CS(0x3, 0x2)
233 #define EUSART0_CS_PD3   SILABS_DBUS_EUSART0_CS(0x3, 0x3)
234 #define EUSART0_RTS_PA0  SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
235 #define EUSART0_RTS_PA1  SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
236 #define EUSART0_RTS_PA2  SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
237 #define EUSART0_RTS_PA3  SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
238 #define EUSART0_RTS_PA4  SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
239 #define EUSART0_RTS_PA5  SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
240 #define EUSART0_RTS_PA6  SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
241 #define EUSART0_RTS_PA7  SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
242 #define EUSART0_RTS_PA8  SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
243 #define EUSART0_RTS_PB0  SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
244 #define EUSART0_RTS_PB1  SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
245 #define EUSART0_RTS_PB2  SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
246 #define EUSART0_RTS_PB3  SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
247 #define EUSART0_RTS_PB4  SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
248 #define EUSART0_RTS_PC0  SILABS_DBUS_EUSART0_RTS(0x2, 0x0)
249 #define EUSART0_RTS_PC1  SILABS_DBUS_EUSART0_RTS(0x2, 0x1)
250 #define EUSART0_RTS_PC2  SILABS_DBUS_EUSART0_RTS(0x2, 0x2)
251 #define EUSART0_RTS_PC3  SILABS_DBUS_EUSART0_RTS(0x2, 0x3)
252 #define EUSART0_RTS_PC4  SILABS_DBUS_EUSART0_RTS(0x2, 0x4)
253 #define EUSART0_RTS_PC5  SILABS_DBUS_EUSART0_RTS(0x2, 0x5)
254 #define EUSART0_RTS_PC6  SILABS_DBUS_EUSART0_RTS(0x2, 0x6)
255 #define EUSART0_RTS_PC7  SILABS_DBUS_EUSART0_RTS(0x2, 0x7)
256 #define EUSART0_RTS_PD0  SILABS_DBUS_EUSART0_RTS(0x3, 0x0)
257 #define EUSART0_RTS_PD1  SILABS_DBUS_EUSART0_RTS(0x3, 0x1)
258 #define EUSART0_RTS_PD2  SILABS_DBUS_EUSART0_RTS(0x3, 0x2)
259 #define EUSART0_RTS_PD3  SILABS_DBUS_EUSART0_RTS(0x3, 0x3)
260 #define EUSART0_RX_PA0   SILABS_DBUS_EUSART0_RX(0x0, 0x0)
261 #define EUSART0_RX_PA1   SILABS_DBUS_EUSART0_RX(0x0, 0x1)
262 #define EUSART0_RX_PA2   SILABS_DBUS_EUSART0_RX(0x0, 0x2)
263 #define EUSART0_RX_PA3   SILABS_DBUS_EUSART0_RX(0x0, 0x3)
264 #define EUSART0_RX_PA4   SILABS_DBUS_EUSART0_RX(0x0, 0x4)
265 #define EUSART0_RX_PA5   SILABS_DBUS_EUSART0_RX(0x0, 0x5)
266 #define EUSART0_RX_PA6   SILABS_DBUS_EUSART0_RX(0x0, 0x6)
267 #define EUSART0_RX_PA7   SILABS_DBUS_EUSART0_RX(0x0, 0x7)
268 #define EUSART0_RX_PA8   SILABS_DBUS_EUSART0_RX(0x0, 0x8)
269 #define EUSART0_RX_PB0   SILABS_DBUS_EUSART0_RX(0x1, 0x0)
270 #define EUSART0_RX_PB1   SILABS_DBUS_EUSART0_RX(0x1, 0x1)
271 #define EUSART0_RX_PB2   SILABS_DBUS_EUSART0_RX(0x1, 0x2)
272 #define EUSART0_RX_PB3   SILABS_DBUS_EUSART0_RX(0x1, 0x3)
273 #define EUSART0_RX_PB4   SILABS_DBUS_EUSART0_RX(0x1, 0x4)
274 #define EUSART0_RX_PC0   SILABS_DBUS_EUSART0_RX(0x2, 0x0)
275 #define EUSART0_RX_PC1   SILABS_DBUS_EUSART0_RX(0x2, 0x1)
276 #define EUSART0_RX_PC2   SILABS_DBUS_EUSART0_RX(0x2, 0x2)
277 #define EUSART0_RX_PC3   SILABS_DBUS_EUSART0_RX(0x2, 0x3)
278 #define EUSART0_RX_PC4   SILABS_DBUS_EUSART0_RX(0x2, 0x4)
279 #define EUSART0_RX_PC5   SILABS_DBUS_EUSART0_RX(0x2, 0x5)
280 #define EUSART0_RX_PC6   SILABS_DBUS_EUSART0_RX(0x2, 0x6)
281 #define EUSART0_RX_PC7   SILABS_DBUS_EUSART0_RX(0x2, 0x7)
282 #define EUSART0_RX_PD0   SILABS_DBUS_EUSART0_RX(0x3, 0x0)
283 #define EUSART0_RX_PD1   SILABS_DBUS_EUSART0_RX(0x3, 0x1)
284 #define EUSART0_RX_PD2   SILABS_DBUS_EUSART0_RX(0x3, 0x2)
285 #define EUSART0_RX_PD3   SILABS_DBUS_EUSART0_RX(0x3, 0x3)
286 #define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
287 #define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
288 #define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
289 #define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
290 #define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
291 #define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
292 #define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
293 #define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
294 #define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
295 #define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
296 #define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
297 #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
298 #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
299 #define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
300 #define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0)
301 #define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1)
302 #define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2)
303 #define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3)
304 #define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4)
305 #define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5)
306 #define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6)
307 #define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7)
308 #define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0)
309 #define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1)
310 #define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2)
311 #define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3)
312 #define EUSART0_TX_PA0   SILABS_DBUS_EUSART0_TX(0x0, 0x0)
313 #define EUSART0_TX_PA1   SILABS_DBUS_EUSART0_TX(0x0, 0x1)
314 #define EUSART0_TX_PA2   SILABS_DBUS_EUSART0_TX(0x0, 0x2)
315 #define EUSART0_TX_PA3   SILABS_DBUS_EUSART0_TX(0x0, 0x3)
316 #define EUSART0_TX_PA4   SILABS_DBUS_EUSART0_TX(0x0, 0x4)
317 #define EUSART0_TX_PA5   SILABS_DBUS_EUSART0_TX(0x0, 0x5)
318 #define EUSART0_TX_PA6   SILABS_DBUS_EUSART0_TX(0x0, 0x6)
319 #define EUSART0_TX_PA7   SILABS_DBUS_EUSART0_TX(0x0, 0x7)
320 #define EUSART0_TX_PA8   SILABS_DBUS_EUSART0_TX(0x0, 0x8)
321 #define EUSART0_TX_PB0   SILABS_DBUS_EUSART0_TX(0x1, 0x0)
322 #define EUSART0_TX_PB1   SILABS_DBUS_EUSART0_TX(0x1, 0x1)
323 #define EUSART0_TX_PB2   SILABS_DBUS_EUSART0_TX(0x1, 0x2)
324 #define EUSART0_TX_PB3   SILABS_DBUS_EUSART0_TX(0x1, 0x3)
325 #define EUSART0_TX_PB4   SILABS_DBUS_EUSART0_TX(0x1, 0x4)
326 #define EUSART0_TX_PC0   SILABS_DBUS_EUSART0_TX(0x2, 0x0)
327 #define EUSART0_TX_PC1   SILABS_DBUS_EUSART0_TX(0x2, 0x1)
328 #define EUSART0_TX_PC2   SILABS_DBUS_EUSART0_TX(0x2, 0x2)
329 #define EUSART0_TX_PC3   SILABS_DBUS_EUSART0_TX(0x2, 0x3)
330 #define EUSART0_TX_PC4   SILABS_DBUS_EUSART0_TX(0x2, 0x4)
331 #define EUSART0_TX_PC5   SILABS_DBUS_EUSART0_TX(0x2, 0x5)
332 #define EUSART0_TX_PC6   SILABS_DBUS_EUSART0_TX(0x2, 0x6)
333 #define EUSART0_TX_PC7   SILABS_DBUS_EUSART0_TX(0x2, 0x7)
334 #define EUSART0_TX_PD0   SILABS_DBUS_EUSART0_TX(0x3, 0x0)
335 #define EUSART0_TX_PD1   SILABS_DBUS_EUSART0_TX(0x3, 0x1)
336 #define EUSART0_TX_PD2   SILABS_DBUS_EUSART0_TX(0x3, 0x2)
337 #define EUSART0_TX_PD3   SILABS_DBUS_EUSART0_TX(0x3, 0x3)
338 #define EUSART0_CTS_PA0  SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
339 #define EUSART0_CTS_PA1  SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
340 #define EUSART0_CTS_PA2  SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
341 #define EUSART0_CTS_PA3  SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
342 #define EUSART0_CTS_PA4  SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
343 #define EUSART0_CTS_PA5  SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
344 #define EUSART0_CTS_PA6  SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
345 #define EUSART0_CTS_PA7  SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
346 #define EUSART0_CTS_PA8  SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
347 #define EUSART0_CTS_PB0  SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
348 #define EUSART0_CTS_PB1  SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
349 #define EUSART0_CTS_PB2  SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
350 #define EUSART0_CTS_PB3  SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
351 #define EUSART0_CTS_PB4  SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
352 #define EUSART0_CTS_PC0  SILABS_DBUS_EUSART0_CTS(0x2, 0x0)
353 #define EUSART0_CTS_PC1  SILABS_DBUS_EUSART0_CTS(0x2, 0x1)
354 #define EUSART0_CTS_PC2  SILABS_DBUS_EUSART0_CTS(0x2, 0x2)
355 #define EUSART0_CTS_PC3  SILABS_DBUS_EUSART0_CTS(0x2, 0x3)
356 #define EUSART0_CTS_PC4  SILABS_DBUS_EUSART0_CTS(0x2, 0x4)
357 #define EUSART0_CTS_PC5  SILABS_DBUS_EUSART0_CTS(0x2, 0x5)
358 #define EUSART0_CTS_PC6  SILABS_DBUS_EUSART0_CTS(0x2, 0x6)
359 #define EUSART0_CTS_PC7  SILABS_DBUS_EUSART0_CTS(0x2, 0x7)
360 #define EUSART0_CTS_PD0  SILABS_DBUS_EUSART0_CTS(0x3, 0x0)
361 #define EUSART0_CTS_PD1  SILABS_DBUS_EUSART0_CTS(0x3, 0x1)
362 #define EUSART0_CTS_PD2  SILABS_DBUS_EUSART0_CTS(0x3, 0x2)
363 #define EUSART0_CTS_PD3  SILABS_DBUS_EUSART0_CTS(0x3, 0x3)
365 #define PTI_DCLK_PC0   SILABS_DBUS_PTI_DCLK(0x2, 0x0)
366 #define PTI_DCLK_PC1   SILABS_DBUS_PTI_DCLK(0x2, 0x1)
367 #define PTI_DCLK_PC2   SILABS_DBUS_PTI_DCLK(0x2, 0x2)
368 #define PTI_DCLK_PC3   SILABS_DBUS_PTI_DCLK(0x2, 0x3)
369 #define PTI_DCLK_PC4   SILABS_DBUS_PTI_DCLK(0x2, 0x4)
370 #define PTI_DCLK_PC5   SILABS_DBUS_PTI_DCLK(0x2, 0x5)
371 #define PTI_DCLK_PC6   SILABS_DBUS_PTI_DCLK(0x2, 0x6)
372 #define PTI_DCLK_PC7   SILABS_DBUS_PTI_DCLK(0x2, 0x7)
373 #define PTI_DCLK_PD0   SILABS_DBUS_PTI_DCLK(0x3, 0x0)
374 #define PTI_DCLK_PD1   SILABS_DBUS_PTI_DCLK(0x3, 0x1)
375 #define PTI_DCLK_PD2   SILABS_DBUS_PTI_DCLK(0x3, 0x2)
376 #define PTI_DCLK_PD3   SILABS_DBUS_PTI_DCLK(0x3, 0x3)
377 #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
378 #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
379 #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
380 #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
381 #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
382 #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
383 #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
384 #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
385 #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
386 #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
387 #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
388 #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
389 #define PTI_DOUT_PC0   SILABS_DBUS_PTI_DOUT(0x2, 0x0)
390 #define PTI_DOUT_PC1   SILABS_DBUS_PTI_DOUT(0x2, 0x1)
391 #define PTI_DOUT_PC2   SILABS_DBUS_PTI_DOUT(0x2, 0x2)
392 #define PTI_DOUT_PC3   SILABS_DBUS_PTI_DOUT(0x2, 0x3)
393 #define PTI_DOUT_PC4   SILABS_DBUS_PTI_DOUT(0x2, 0x4)
394 #define PTI_DOUT_PC5   SILABS_DBUS_PTI_DOUT(0x2, 0x5)
395 #define PTI_DOUT_PC6   SILABS_DBUS_PTI_DOUT(0x2, 0x6)
396 #define PTI_DOUT_PC7   SILABS_DBUS_PTI_DOUT(0x2, 0x7)
397 #define PTI_DOUT_PD0   SILABS_DBUS_PTI_DOUT(0x3, 0x0)
398 #define PTI_DOUT_PD1   SILABS_DBUS_PTI_DOUT(0x3, 0x1)
399 #define PTI_DOUT_PD2   SILABS_DBUS_PTI_DOUT(0x3, 0x2)
400 #define PTI_DOUT_PD3   SILABS_DBUS_PTI_DOUT(0x3, 0x3)
402 #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
403 #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
404 #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
405 #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
406 #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
407 #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
408 #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
409 #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
410 #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
411 #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
412 #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
413 #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
414 #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
415 #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
416 #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
417 #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
418 #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
419 #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
420 #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
421 #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
422 #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
423 #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
424 #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
425 #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
426 #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
427 #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
428 #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
429 #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
430 #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
431 #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
432 #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
433 #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
434 #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
435 #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
436 #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
437 #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
438 #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
439 #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
440 #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
441 #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
442 #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
443 #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
444 #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
445 #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
446 #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
447 #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
448 #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
449 #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
450 #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
451 #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
452 #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
453 #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
455 #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
456 #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
457 #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
458 #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
459 #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
460 #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
461 #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
462 #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
463 #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
464 #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
465 #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
466 #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
467 #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
468 #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
469 #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
470 #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
471 #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
472 #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
473 #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
474 #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
475 #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
476 #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
477 #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
478 #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
480 #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
481 #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
482 #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
483 #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
484 #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
485 #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
486 #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
487 #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
488 #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
489 #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
490 #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
491 #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
492 #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
493 #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
494 #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
495 #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
496 #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
497 #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
498 #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
499 #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
500 #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
501 #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
502 #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
503 #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
504 #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
505 #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
506 #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
507 #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
509 #define MODEM_ANT0_PA0        SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
510 #define MODEM_ANT0_PA1        SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
511 #define MODEM_ANT0_PA2        SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
512 #define MODEM_ANT0_PA3        SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
513 #define MODEM_ANT0_PA4        SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
514 #define MODEM_ANT0_PA5        SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
515 #define MODEM_ANT0_PA6        SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
516 #define MODEM_ANT0_PA7        SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
517 #define MODEM_ANT0_PA8        SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
518 #define MODEM_ANT0_PB0        SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
519 #define MODEM_ANT0_PB1        SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
520 #define MODEM_ANT0_PB2        SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
521 #define MODEM_ANT0_PB3        SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
522 #define MODEM_ANT0_PB4        SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
523 #define MODEM_ANT0_PC0        SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
524 #define MODEM_ANT0_PC1        SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
525 #define MODEM_ANT0_PC2        SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
526 #define MODEM_ANT0_PC3        SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
527 #define MODEM_ANT0_PC4        SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
528 #define MODEM_ANT0_PC5        SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
529 #define MODEM_ANT0_PC6        SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
530 #define MODEM_ANT0_PC7        SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
531 #define MODEM_ANT0_PD0        SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
532 #define MODEM_ANT0_PD1        SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
533 #define MODEM_ANT0_PD2        SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
534 #define MODEM_ANT0_PD3        SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
535 #define MODEM_ANT1_PA0        SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
536 #define MODEM_ANT1_PA1        SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
537 #define MODEM_ANT1_PA2        SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
538 #define MODEM_ANT1_PA3        SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
539 #define MODEM_ANT1_PA4        SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
540 #define MODEM_ANT1_PA5        SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
541 #define MODEM_ANT1_PA6        SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
542 #define MODEM_ANT1_PA7        SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
543 #define MODEM_ANT1_PA8        SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
544 #define MODEM_ANT1_PB0        SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
545 #define MODEM_ANT1_PB1        SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
546 #define MODEM_ANT1_PB2        SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
547 #define MODEM_ANT1_PB3        SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
548 #define MODEM_ANT1_PB4        SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
549 #define MODEM_ANT1_PC0        SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
550 #define MODEM_ANT1_PC1        SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
551 #define MODEM_ANT1_PC2        SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
552 #define MODEM_ANT1_PC3        SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
553 #define MODEM_ANT1_PC4        SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
554 #define MODEM_ANT1_PC5        SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
555 #define MODEM_ANT1_PC6        SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
556 #define MODEM_ANT1_PC7        SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
557 #define MODEM_ANT1_PD0        SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
558 #define MODEM_ANT1_PD1        SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
559 #define MODEM_ANT1_PD2        SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
560 #define MODEM_ANT1_PD3        SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
561 #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
562 #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
563 #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
564 #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
565 #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
566 #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
567 #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
568 #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
569 #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
570 #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
571 #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
572 #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
573 #define MODEM_ANTRR0_PC0      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
574 #define MODEM_ANTRR0_PC1      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
575 #define MODEM_ANTRR0_PC2      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
576 #define MODEM_ANTRR0_PC3      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
577 #define MODEM_ANTRR0_PC4      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
578 #define MODEM_ANTRR0_PC5      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
579 #define MODEM_ANTRR0_PC6      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
580 #define MODEM_ANTRR0_PC7      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
581 #define MODEM_ANTRR0_PD0      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
582 #define MODEM_ANTRR0_PD1      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
583 #define MODEM_ANTRR0_PD2      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
584 #define MODEM_ANTRR0_PD3      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
585 #define MODEM_ANTRR1_PC0      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
586 #define MODEM_ANTRR1_PC1      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
587 #define MODEM_ANTRR1_PC2      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
588 #define MODEM_ANTRR1_PC3      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
589 #define MODEM_ANTRR1_PC4      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
590 #define MODEM_ANTRR1_PC5      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
591 #define MODEM_ANTRR1_PC6      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
592 #define MODEM_ANTRR1_PC7      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
593 #define MODEM_ANTRR1_PD0      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
594 #define MODEM_ANTRR1_PD1      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
595 #define MODEM_ANTRR1_PD2      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
596 #define MODEM_ANTRR1_PD3      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
597 #define MODEM_ANTRR2_PC0      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
598 #define MODEM_ANTRR2_PC1      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
599 #define MODEM_ANTRR2_PC2      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
600 #define MODEM_ANTRR2_PC3      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
601 #define MODEM_ANTRR2_PC4      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
602 #define MODEM_ANTRR2_PC5      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
603 #define MODEM_ANTRR2_PC6      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
604 #define MODEM_ANTRR2_PC7      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
605 #define MODEM_ANTRR2_PD0      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
606 #define MODEM_ANTRR2_PD1      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
607 #define MODEM_ANTRR2_PD2      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
608 #define MODEM_ANTRR2_PD3      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
609 #define MODEM_ANTRR3_PC0      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
610 #define MODEM_ANTRR3_PC1      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
611 #define MODEM_ANTRR3_PC2      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
612 #define MODEM_ANTRR3_PC3      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
613 #define MODEM_ANTRR3_PC4      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
614 #define MODEM_ANTRR3_PC5      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
615 #define MODEM_ANTRR3_PC6      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
616 #define MODEM_ANTRR3_PC7      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
617 #define MODEM_ANTRR3_PD0      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
618 #define MODEM_ANTRR3_PD1      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
619 #define MODEM_ANTRR3_PD2      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
620 #define MODEM_ANTRR3_PD3      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
621 #define MODEM_ANTRR4_PC0      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
622 #define MODEM_ANTRR4_PC1      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
623 #define MODEM_ANTRR4_PC2      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
624 #define MODEM_ANTRR4_PC3      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
625 #define MODEM_ANTRR4_PC4      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
626 #define MODEM_ANTRR4_PC5      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
627 #define MODEM_ANTRR4_PC6      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
628 #define MODEM_ANTRR4_PC7      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
629 #define MODEM_ANTRR4_PD0      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
630 #define MODEM_ANTRR4_PD1      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
631 #define MODEM_ANTRR4_PD2      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
632 #define MODEM_ANTRR4_PD3      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
633 #define MODEM_ANTRR5_PC0      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
634 #define MODEM_ANTRR5_PC1      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
635 #define MODEM_ANTRR5_PC2      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
636 #define MODEM_ANTRR5_PC3      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
637 #define MODEM_ANTRR5_PC4      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
638 #define MODEM_ANTRR5_PC5      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
639 #define MODEM_ANTRR5_PC6      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
640 #define MODEM_ANTRR5_PC7      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
641 #define MODEM_ANTRR5_PD0      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
642 #define MODEM_ANTRR5_PD1      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
643 #define MODEM_ANTRR5_PD2      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
644 #define MODEM_ANTRR5_PD3      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
645 #define MODEM_ANTSWEN_PC0     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
646 #define MODEM_ANTSWEN_PC1     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
647 #define MODEM_ANTSWEN_PC2     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
648 #define MODEM_ANTSWEN_PC3     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
649 #define MODEM_ANTSWEN_PC4     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
650 #define MODEM_ANTSWEN_PC5     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
651 #define MODEM_ANTSWEN_PC6     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
652 #define MODEM_ANTSWEN_PC7     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
653 #define MODEM_ANTSWEN_PD0     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
654 #define MODEM_ANTSWEN_PD1     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
655 #define MODEM_ANTSWEN_PD2     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
656 #define MODEM_ANTSWEN_PD3     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
657 #define MODEM_ANTSWUS_PC0     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
658 #define MODEM_ANTSWUS_PC1     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
659 #define MODEM_ANTSWUS_PC2     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
660 #define MODEM_ANTSWUS_PC3     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
661 #define MODEM_ANTSWUS_PC4     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
662 #define MODEM_ANTSWUS_PC5     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
663 #define MODEM_ANTSWUS_PC6     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
664 #define MODEM_ANTSWUS_PC7     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
665 #define MODEM_ANTSWUS_PD0     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
666 #define MODEM_ANTSWUS_PD1     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
667 #define MODEM_ANTSWUS_PD2     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
668 #define MODEM_ANTSWUS_PD3     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
669 #define MODEM_ANTTRIG_PC0     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
670 #define MODEM_ANTTRIG_PC1     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
671 #define MODEM_ANTTRIG_PC2     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
672 #define MODEM_ANTTRIG_PC3     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
673 #define MODEM_ANTTRIG_PC4     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
674 #define MODEM_ANTTRIG_PC5     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
675 #define MODEM_ANTTRIG_PC6     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
676 #define MODEM_ANTTRIG_PC7     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
677 #define MODEM_ANTTRIG_PD0     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
678 #define MODEM_ANTTRIG_PD1     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
679 #define MODEM_ANTTRIG_PD2     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
680 #define MODEM_ANTTRIG_PD3     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
681 #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
682 #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
683 #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
684 #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
685 #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
686 #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
687 #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
688 #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
689 #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
690 #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
691 #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
692 #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
693 #define MODEM_DCLK_PA0        SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
694 #define MODEM_DCLK_PA1        SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
695 #define MODEM_DCLK_PA2        SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
696 #define MODEM_DCLK_PA3        SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
697 #define MODEM_DCLK_PA4        SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
698 #define MODEM_DCLK_PA5        SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
699 #define MODEM_DCLK_PA6        SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
700 #define MODEM_DCLK_PA7        SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
701 #define MODEM_DCLK_PA8        SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
702 #define MODEM_DCLK_PB0        SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
703 #define MODEM_DCLK_PB1        SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
704 #define MODEM_DCLK_PB2        SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
705 #define MODEM_DCLK_PB3        SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
706 #define MODEM_DCLK_PB4        SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
707 #define MODEM_DOUT_PA0        SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
708 #define MODEM_DOUT_PA1        SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
709 #define MODEM_DOUT_PA2        SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
710 #define MODEM_DOUT_PA3        SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
711 #define MODEM_DOUT_PA4        SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
712 #define MODEM_DOUT_PA5        SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
713 #define MODEM_DOUT_PA6        SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
714 #define MODEM_DOUT_PA7        SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
715 #define MODEM_DOUT_PA8        SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
716 #define MODEM_DOUT_PB0        SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
717 #define MODEM_DOUT_PB1        SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
718 #define MODEM_DOUT_PB2        SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
719 #define MODEM_DOUT_PB3        SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
720 #define MODEM_DOUT_PB4        SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
721 #define MODEM_DIN_PA0         SILABS_DBUS_MODEM_DIN(0x0, 0x0)
722 #define MODEM_DIN_PA1         SILABS_DBUS_MODEM_DIN(0x0, 0x1)
723 #define MODEM_DIN_PA2         SILABS_DBUS_MODEM_DIN(0x0, 0x2)
724 #define MODEM_DIN_PA3         SILABS_DBUS_MODEM_DIN(0x0, 0x3)
725 #define MODEM_DIN_PA4         SILABS_DBUS_MODEM_DIN(0x0, 0x4)
726 #define MODEM_DIN_PA5         SILABS_DBUS_MODEM_DIN(0x0, 0x5)
727 #define MODEM_DIN_PA6         SILABS_DBUS_MODEM_DIN(0x0, 0x6)
728 #define MODEM_DIN_PA7         SILABS_DBUS_MODEM_DIN(0x0, 0x7)
729 #define MODEM_DIN_PA8         SILABS_DBUS_MODEM_DIN(0x0, 0x8)
730 #define MODEM_DIN_PB0         SILABS_DBUS_MODEM_DIN(0x1, 0x0)
731 #define MODEM_DIN_PB1         SILABS_DBUS_MODEM_DIN(0x1, 0x1)
732 #define MODEM_DIN_PB2         SILABS_DBUS_MODEM_DIN(0x1, 0x2)
733 #define MODEM_DIN_PB3         SILABS_DBUS_MODEM_DIN(0x1, 0x3)
734 #define MODEM_DIN_PB4         SILABS_DBUS_MODEM_DIN(0x1, 0x4)
736 #define PDM_CLK_PA0  SILABS_DBUS_PDM_CLK(0x0, 0x0)
737 #define PDM_CLK_PA1  SILABS_DBUS_PDM_CLK(0x0, 0x1)
738 #define PDM_CLK_PA2  SILABS_DBUS_PDM_CLK(0x0, 0x2)
739 #define PDM_CLK_PA3  SILABS_DBUS_PDM_CLK(0x0, 0x3)
740 #define PDM_CLK_PA4  SILABS_DBUS_PDM_CLK(0x0, 0x4)
741 #define PDM_CLK_PA5  SILABS_DBUS_PDM_CLK(0x0, 0x5)
742 #define PDM_CLK_PA6  SILABS_DBUS_PDM_CLK(0x0, 0x6)
743 #define PDM_CLK_PA7  SILABS_DBUS_PDM_CLK(0x0, 0x7)
744 #define PDM_CLK_PA8  SILABS_DBUS_PDM_CLK(0x0, 0x8)
745 #define PDM_CLK_PB0  SILABS_DBUS_PDM_CLK(0x1, 0x0)
746 #define PDM_CLK_PB1  SILABS_DBUS_PDM_CLK(0x1, 0x1)
747 #define PDM_CLK_PB2  SILABS_DBUS_PDM_CLK(0x1, 0x2)
748 #define PDM_CLK_PB3  SILABS_DBUS_PDM_CLK(0x1, 0x3)
749 #define PDM_CLK_PB4  SILABS_DBUS_PDM_CLK(0x1, 0x4)
750 #define PDM_CLK_PC0  SILABS_DBUS_PDM_CLK(0x2, 0x0)
751 #define PDM_CLK_PC1  SILABS_DBUS_PDM_CLK(0x2, 0x1)
752 #define PDM_CLK_PC2  SILABS_DBUS_PDM_CLK(0x2, 0x2)
753 #define PDM_CLK_PC3  SILABS_DBUS_PDM_CLK(0x2, 0x3)
754 #define PDM_CLK_PC4  SILABS_DBUS_PDM_CLK(0x2, 0x4)
755 #define PDM_CLK_PC5  SILABS_DBUS_PDM_CLK(0x2, 0x5)
756 #define PDM_CLK_PC6  SILABS_DBUS_PDM_CLK(0x2, 0x6)
757 #define PDM_CLK_PC7  SILABS_DBUS_PDM_CLK(0x2, 0x7)
758 #define PDM_CLK_PD0  SILABS_DBUS_PDM_CLK(0x3, 0x0)
759 #define PDM_CLK_PD1  SILABS_DBUS_PDM_CLK(0x3, 0x1)
760 #define PDM_CLK_PD2  SILABS_DBUS_PDM_CLK(0x3, 0x2)
761 #define PDM_CLK_PD3  SILABS_DBUS_PDM_CLK(0x3, 0x3)
762 #define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0)
763 #define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
764 #define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
765 #define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
766 #define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4)
767 #define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
768 #define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
769 #define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7)
770 #define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
771 #define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
772 #define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
773 #define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
774 #define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
775 #define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
776 #define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
777 #define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
778 #define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
779 #define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
780 #define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
781 #define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
782 #define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
783 #define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
784 #define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
785 #define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
786 #define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
787 #define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
788 #define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0)
789 #define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
790 #define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
791 #define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
792 #define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4)
793 #define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
794 #define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
795 #define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7)
796 #define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
797 #define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
798 #define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
799 #define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
800 #define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
801 #define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
802 #define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
803 #define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
804 #define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
805 #define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
806 #define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
807 #define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
808 #define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
809 #define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
810 #define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
811 #define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
812 #define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
813 #define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
815 #define PRS0_ASYNCH0_PA0  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
816 #define PRS0_ASYNCH0_PA1  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
817 #define PRS0_ASYNCH0_PA2  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
818 #define PRS0_ASYNCH0_PA3  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
819 #define PRS0_ASYNCH0_PA4  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
820 #define PRS0_ASYNCH0_PA5  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
821 #define PRS0_ASYNCH0_PA6  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
822 #define PRS0_ASYNCH0_PA7  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
823 #define PRS0_ASYNCH0_PA8  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
824 #define PRS0_ASYNCH0_PB0  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
825 #define PRS0_ASYNCH0_PB1  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
826 #define PRS0_ASYNCH0_PB2  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
827 #define PRS0_ASYNCH0_PB3  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
828 #define PRS0_ASYNCH0_PB4  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
829 #define PRS0_ASYNCH1_PA0  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
830 #define PRS0_ASYNCH1_PA1  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
831 #define PRS0_ASYNCH1_PA2  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
832 #define PRS0_ASYNCH1_PA3  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
833 #define PRS0_ASYNCH1_PA4  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
834 #define PRS0_ASYNCH1_PA5  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
835 #define PRS0_ASYNCH1_PA6  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
836 #define PRS0_ASYNCH1_PA7  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
837 #define PRS0_ASYNCH1_PA8  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
838 #define PRS0_ASYNCH1_PB0  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
839 #define PRS0_ASYNCH1_PB1  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
840 #define PRS0_ASYNCH1_PB2  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
841 #define PRS0_ASYNCH1_PB3  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
842 #define PRS0_ASYNCH1_PB4  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
843 #define PRS0_ASYNCH2_PA0  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
844 #define PRS0_ASYNCH2_PA1  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
845 #define PRS0_ASYNCH2_PA2  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
846 #define PRS0_ASYNCH2_PA3  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
847 #define PRS0_ASYNCH2_PA4  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
848 #define PRS0_ASYNCH2_PA5  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
849 #define PRS0_ASYNCH2_PA6  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
850 #define PRS0_ASYNCH2_PA7  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
851 #define PRS0_ASYNCH2_PA8  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
852 #define PRS0_ASYNCH2_PB0  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
853 #define PRS0_ASYNCH2_PB1  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
854 #define PRS0_ASYNCH2_PB2  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
855 #define PRS0_ASYNCH2_PB3  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
856 #define PRS0_ASYNCH2_PB4  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
857 #define PRS0_ASYNCH3_PA0  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
858 #define PRS0_ASYNCH3_PA1  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
859 #define PRS0_ASYNCH3_PA2  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
860 #define PRS0_ASYNCH3_PA3  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
861 #define PRS0_ASYNCH3_PA4  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
862 #define PRS0_ASYNCH3_PA5  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
863 #define PRS0_ASYNCH3_PA6  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
864 #define PRS0_ASYNCH3_PA7  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
865 #define PRS0_ASYNCH3_PA8  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
866 #define PRS0_ASYNCH3_PB0  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
867 #define PRS0_ASYNCH3_PB1  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
868 #define PRS0_ASYNCH3_PB2  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
869 #define PRS0_ASYNCH3_PB3  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
870 #define PRS0_ASYNCH3_PB4  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
871 #define PRS0_ASYNCH4_PA0  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
872 #define PRS0_ASYNCH4_PA1  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
873 #define PRS0_ASYNCH4_PA2  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
874 #define PRS0_ASYNCH4_PA3  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
875 #define PRS0_ASYNCH4_PA4  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
876 #define PRS0_ASYNCH4_PA5  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
877 #define PRS0_ASYNCH4_PA6  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
878 #define PRS0_ASYNCH4_PA7  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
879 #define PRS0_ASYNCH4_PA8  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
880 #define PRS0_ASYNCH4_PB0  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
881 #define PRS0_ASYNCH4_PB1  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
882 #define PRS0_ASYNCH4_PB2  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
883 #define PRS0_ASYNCH4_PB3  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
884 #define PRS0_ASYNCH4_PB4  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
885 #define PRS0_ASYNCH5_PA0  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
886 #define PRS0_ASYNCH5_PA1  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
887 #define PRS0_ASYNCH5_PA2  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
888 #define PRS0_ASYNCH5_PA3  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
889 #define PRS0_ASYNCH5_PA4  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
890 #define PRS0_ASYNCH5_PA5  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
891 #define PRS0_ASYNCH5_PA6  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
892 #define PRS0_ASYNCH5_PA7  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
893 #define PRS0_ASYNCH5_PA8  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
894 #define PRS0_ASYNCH5_PB0  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
895 #define PRS0_ASYNCH5_PB1  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
896 #define PRS0_ASYNCH5_PB2  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
897 #define PRS0_ASYNCH5_PB3  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
898 #define PRS0_ASYNCH5_PB4  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
899 #define PRS0_ASYNCH6_PC0  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
900 #define PRS0_ASYNCH6_PC1  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
901 #define PRS0_ASYNCH6_PC2  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
902 #define PRS0_ASYNCH6_PC3  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
903 #define PRS0_ASYNCH6_PC4  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
904 #define PRS0_ASYNCH6_PC5  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
905 #define PRS0_ASYNCH6_PC6  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
906 #define PRS0_ASYNCH6_PC7  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
907 #define PRS0_ASYNCH6_PD0  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
908 #define PRS0_ASYNCH6_PD1  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
909 #define PRS0_ASYNCH6_PD2  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
910 #define PRS0_ASYNCH6_PD3  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
911 #define PRS0_ASYNCH7_PC0  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
912 #define PRS0_ASYNCH7_PC1  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
913 #define PRS0_ASYNCH7_PC2  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
914 #define PRS0_ASYNCH7_PC3  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
915 #define PRS0_ASYNCH7_PC4  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
916 #define PRS0_ASYNCH7_PC5  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
917 #define PRS0_ASYNCH7_PC6  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
918 #define PRS0_ASYNCH7_PC7  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
919 #define PRS0_ASYNCH7_PD0  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
920 #define PRS0_ASYNCH7_PD1  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
921 #define PRS0_ASYNCH7_PD2  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
922 #define PRS0_ASYNCH7_PD3  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
923 #define PRS0_ASYNCH8_PC0  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
924 #define PRS0_ASYNCH8_PC1  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
925 #define PRS0_ASYNCH8_PC2  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
926 #define PRS0_ASYNCH8_PC3  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
927 #define PRS0_ASYNCH8_PC4  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
928 #define PRS0_ASYNCH8_PC5  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
929 #define PRS0_ASYNCH8_PC6  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
930 #define PRS0_ASYNCH8_PC7  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
931 #define PRS0_ASYNCH8_PD0  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
932 #define PRS0_ASYNCH8_PD1  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
933 #define PRS0_ASYNCH8_PD2  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
934 #define PRS0_ASYNCH8_PD3  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
935 #define PRS0_ASYNCH9_PC0  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
936 #define PRS0_ASYNCH9_PC1  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
937 #define PRS0_ASYNCH9_PC2  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
938 #define PRS0_ASYNCH9_PC3  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
939 #define PRS0_ASYNCH9_PC4  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
940 #define PRS0_ASYNCH9_PC5  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
941 #define PRS0_ASYNCH9_PC6  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
942 #define PRS0_ASYNCH9_PC7  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
943 #define PRS0_ASYNCH9_PD0  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
944 #define PRS0_ASYNCH9_PD1  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
945 #define PRS0_ASYNCH9_PD2  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
946 #define PRS0_ASYNCH9_PD3  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
947 #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
948 #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
949 #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
950 #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
951 #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
952 #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
953 #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
954 #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
955 #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
956 #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
957 #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
958 #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
959 #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
960 #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
961 #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
962 #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
963 #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
964 #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
965 #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
966 #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
967 #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
968 #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
969 #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
970 #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
971 #define PRS0_SYNCH0_PA0   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
972 #define PRS0_SYNCH0_PA1   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
973 #define PRS0_SYNCH0_PA2   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
974 #define PRS0_SYNCH0_PA3   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
975 #define PRS0_SYNCH0_PA4   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
976 #define PRS0_SYNCH0_PA5   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
977 #define PRS0_SYNCH0_PA6   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
978 #define PRS0_SYNCH0_PA7   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
979 #define PRS0_SYNCH0_PA8   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
980 #define PRS0_SYNCH0_PB0   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
981 #define PRS0_SYNCH0_PB1   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
982 #define PRS0_SYNCH0_PB2   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
983 #define PRS0_SYNCH0_PB3   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
984 #define PRS0_SYNCH0_PB4   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
985 #define PRS0_SYNCH0_PC0   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
986 #define PRS0_SYNCH0_PC1   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
987 #define PRS0_SYNCH0_PC2   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
988 #define PRS0_SYNCH0_PC3   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
989 #define PRS0_SYNCH0_PC4   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
990 #define PRS0_SYNCH0_PC5   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
991 #define PRS0_SYNCH0_PC6   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
992 #define PRS0_SYNCH0_PC7   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
993 #define PRS0_SYNCH0_PD0   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
994 #define PRS0_SYNCH0_PD1   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
995 #define PRS0_SYNCH0_PD2   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
996 #define PRS0_SYNCH0_PD3   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
997 #define PRS0_SYNCH1_PA0   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
998 #define PRS0_SYNCH1_PA1   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
999 #define PRS0_SYNCH1_PA2   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
1000 #define PRS0_SYNCH1_PA3   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
1001 #define PRS0_SYNCH1_PA4   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
1002 #define PRS0_SYNCH1_PA5   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
1003 #define PRS0_SYNCH1_PA6   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
1004 #define PRS0_SYNCH1_PA7   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
1005 #define PRS0_SYNCH1_PA8   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
1006 #define PRS0_SYNCH1_PB0   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
1007 #define PRS0_SYNCH1_PB1   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
1008 #define PRS0_SYNCH1_PB2   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
1009 #define PRS0_SYNCH1_PB3   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
1010 #define PRS0_SYNCH1_PB4   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
1011 #define PRS0_SYNCH1_PC0   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
1012 #define PRS0_SYNCH1_PC1   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
1013 #define PRS0_SYNCH1_PC2   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
1014 #define PRS0_SYNCH1_PC3   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
1015 #define PRS0_SYNCH1_PC4   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
1016 #define PRS0_SYNCH1_PC5   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
1017 #define PRS0_SYNCH1_PC6   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
1018 #define PRS0_SYNCH1_PC7   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
1019 #define PRS0_SYNCH1_PD0   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
1020 #define PRS0_SYNCH1_PD1   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
1021 #define PRS0_SYNCH1_PD2   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
1022 #define PRS0_SYNCH1_PD3   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
1023 #define PRS0_SYNCH2_PA0   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
1024 #define PRS0_SYNCH2_PA1   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
1025 #define PRS0_SYNCH2_PA2   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
1026 #define PRS0_SYNCH2_PA3   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
1027 #define PRS0_SYNCH2_PA4   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
1028 #define PRS0_SYNCH2_PA5   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
1029 #define PRS0_SYNCH2_PA6   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
1030 #define PRS0_SYNCH2_PA7   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
1031 #define PRS0_SYNCH2_PA8   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
1032 #define PRS0_SYNCH2_PB0   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
1033 #define PRS0_SYNCH2_PB1   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
1034 #define PRS0_SYNCH2_PB2   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
1035 #define PRS0_SYNCH2_PB3   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
1036 #define PRS0_SYNCH2_PB4   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
1037 #define PRS0_SYNCH2_PC0   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
1038 #define PRS0_SYNCH2_PC1   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
1039 #define PRS0_SYNCH2_PC2   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
1040 #define PRS0_SYNCH2_PC3   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
1041 #define PRS0_SYNCH2_PC4   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
1042 #define PRS0_SYNCH2_PC5   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
1043 #define PRS0_SYNCH2_PC6   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
1044 #define PRS0_SYNCH2_PC7   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
1045 #define PRS0_SYNCH2_PD0   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
1046 #define PRS0_SYNCH2_PD1   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
1047 #define PRS0_SYNCH2_PD2   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
1048 #define PRS0_SYNCH2_PD3   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
1049 #define PRS0_SYNCH3_PA0   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
1050 #define PRS0_SYNCH3_PA1   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
1051 #define PRS0_SYNCH3_PA2   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
1052 #define PRS0_SYNCH3_PA3   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
1053 #define PRS0_SYNCH3_PA4   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
1054 #define PRS0_SYNCH3_PA5   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
1055 #define PRS0_SYNCH3_PA6   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
1056 #define PRS0_SYNCH3_PA7   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
1057 #define PRS0_SYNCH3_PA8   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
1058 #define PRS0_SYNCH3_PB0   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
1059 #define PRS0_SYNCH3_PB1   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
1060 #define PRS0_SYNCH3_PB2   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
1061 #define PRS0_SYNCH3_PB3   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
1062 #define PRS0_SYNCH3_PB4   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
1063 #define PRS0_SYNCH3_PC0   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
1064 #define PRS0_SYNCH3_PC1   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
1065 #define PRS0_SYNCH3_PC2   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
1066 #define PRS0_SYNCH3_PC3   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
1067 #define PRS0_SYNCH3_PC4   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
1068 #define PRS0_SYNCH3_PC5   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
1069 #define PRS0_SYNCH3_PC6   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
1070 #define PRS0_SYNCH3_PC7   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
1071 #define PRS0_SYNCH3_PD0   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
1072 #define PRS0_SYNCH3_PD1   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
1073 #define PRS0_SYNCH3_PD2   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
1074 #define PRS0_SYNCH3_PD3   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
1076 #define TIMER0_CC0_PA0   SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
1077 #define TIMER0_CC0_PA1   SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
1078 #define TIMER0_CC0_PA2   SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
1079 #define TIMER0_CC0_PA3   SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
1080 #define TIMER0_CC0_PA4   SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
1081 #define TIMER0_CC0_PA5   SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
1082 #define TIMER0_CC0_PA6   SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
1083 #define TIMER0_CC0_PA7   SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
1084 #define TIMER0_CC0_PA8   SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1085 #define TIMER0_CC0_PB0   SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
1086 #define TIMER0_CC0_PB1   SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
1087 #define TIMER0_CC0_PB2   SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1088 #define TIMER0_CC0_PB3   SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1089 #define TIMER0_CC0_PB4   SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
1090 #define TIMER0_CC0_PC0   SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1091 #define TIMER0_CC0_PC1   SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1092 #define TIMER0_CC0_PC2   SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1093 #define TIMER0_CC0_PC3   SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1094 #define TIMER0_CC0_PC4   SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1095 #define TIMER0_CC0_PC5   SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1096 #define TIMER0_CC0_PC6   SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1097 #define TIMER0_CC0_PC7   SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1098 #define TIMER0_CC0_PD0   SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
1099 #define TIMER0_CC0_PD1   SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1100 #define TIMER0_CC0_PD2   SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1101 #define TIMER0_CC0_PD3   SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
1102 #define TIMER0_CC1_PA0   SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
1103 #define TIMER0_CC1_PA1   SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
1104 #define TIMER0_CC1_PA2   SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1105 #define TIMER0_CC1_PA3   SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
1106 #define TIMER0_CC1_PA4   SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
1107 #define TIMER0_CC1_PA5   SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
1108 #define TIMER0_CC1_PA6   SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
1109 #define TIMER0_CC1_PA7   SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
1110 #define TIMER0_CC1_PA8   SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1111 #define TIMER0_CC1_PB0   SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
1112 #define TIMER0_CC1_PB1   SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
1113 #define TIMER0_CC1_PB2   SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1114 #define TIMER0_CC1_PB3   SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1115 #define TIMER0_CC1_PB4   SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
1116 #define TIMER0_CC1_PC0   SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1117 #define TIMER0_CC1_PC1   SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1118 #define TIMER0_CC1_PC2   SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1119 #define TIMER0_CC1_PC3   SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1120 #define TIMER0_CC1_PC4   SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1121 #define TIMER0_CC1_PC5   SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1122 #define TIMER0_CC1_PC6   SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1123 #define TIMER0_CC1_PC7   SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1124 #define TIMER0_CC1_PD0   SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
1125 #define TIMER0_CC1_PD1   SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1126 #define TIMER0_CC1_PD2   SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1127 #define TIMER0_CC1_PD3   SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
1128 #define TIMER0_CC2_PA0   SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
1129 #define TIMER0_CC2_PA1   SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
1130 #define TIMER0_CC2_PA2   SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1131 #define TIMER0_CC2_PA3   SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
1132 #define TIMER0_CC2_PA4   SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
1133 #define TIMER0_CC2_PA5   SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
1134 #define TIMER0_CC2_PA6   SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
1135 #define TIMER0_CC2_PA7   SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
1136 #define TIMER0_CC2_PA8   SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1137 #define TIMER0_CC2_PB0   SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
1138 #define TIMER0_CC2_PB1   SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
1139 #define TIMER0_CC2_PB2   SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1140 #define TIMER0_CC2_PB3   SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1141 #define TIMER0_CC2_PB4   SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
1142 #define TIMER0_CC2_PC0   SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1143 #define TIMER0_CC2_PC1   SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1144 #define TIMER0_CC2_PC2   SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1145 #define TIMER0_CC2_PC3   SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1146 #define TIMER0_CC2_PC4   SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1147 #define TIMER0_CC2_PC5   SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1148 #define TIMER0_CC2_PC6   SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1149 #define TIMER0_CC2_PC7   SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1150 #define TIMER0_CC2_PD0   SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
1151 #define TIMER0_CC2_PD1   SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1152 #define TIMER0_CC2_PD2   SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1153 #define TIMER0_CC2_PD3   SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
1154 #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
1155 #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
1156 #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1157 #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
1158 #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
1159 #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
1160 #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
1161 #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
1162 #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1163 #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
1164 #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
1165 #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1166 #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1167 #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
1168 #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1169 #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1170 #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1171 #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1172 #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1173 #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1174 #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1175 #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1176 #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
1177 #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1178 #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1179 #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
1180 #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
1181 #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
1182 #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1183 #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
1184 #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
1185 #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
1186 #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
1187 #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
1188 #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1189 #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
1190 #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
1191 #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1192 #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1193 #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
1194 #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1195 #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1196 #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1197 #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1198 #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1199 #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1200 #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1201 #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1202 #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
1203 #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1204 #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1205 #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
1206 #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
1207 #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
1208 #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
1209 #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
1210 #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
1211 #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
1212 #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
1213 #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
1214 #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
1215 #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
1216 #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
1217 #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
1218 #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
1219 #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
1220 #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
1221 #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
1222 #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
1223 #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
1224 #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
1225 #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
1226 #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
1227 #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
1228 #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
1229 #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
1230 #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
1231 #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
1233 #define TIMER1_CC0_PA0   SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
1234 #define TIMER1_CC0_PA1   SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
1235 #define TIMER1_CC0_PA2   SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
1236 #define TIMER1_CC0_PA3   SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
1237 #define TIMER1_CC0_PA4   SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
1238 #define TIMER1_CC0_PA5   SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
1239 #define TIMER1_CC0_PA6   SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
1240 #define TIMER1_CC0_PA7   SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
1241 #define TIMER1_CC0_PA8   SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
1242 #define TIMER1_CC0_PB0   SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
1243 #define TIMER1_CC0_PB1   SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
1244 #define TIMER1_CC0_PB2   SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
1245 #define TIMER1_CC0_PB3   SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
1246 #define TIMER1_CC0_PB4   SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
1247 #define TIMER1_CC0_PC0   SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
1248 #define TIMER1_CC0_PC1   SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
1249 #define TIMER1_CC0_PC2   SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
1250 #define TIMER1_CC0_PC3   SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
1251 #define TIMER1_CC0_PC4   SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
1252 #define TIMER1_CC0_PC5   SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
1253 #define TIMER1_CC0_PC6   SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
1254 #define TIMER1_CC0_PC7   SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
1255 #define TIMER1_CC0_PD0   SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
1256 #define TIMER1_CC0_PD1   SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
1257 #define TIMER1_CC0_PD2   SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
1258 #define TIMER1_CC0_PD3   SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
1259 #define TIMER1_CC1_PA0   SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
1260 #define TIMER1_CC1_PA1   SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
1261 #define TIMER1_CC1_PA2   SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
1262 #define TIMER1_CC1_PA3   SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
1263 #define TIMER1_CC1_PA4   SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
1264 #define TIMER1_CC1_PA5   SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
1265 #define TIMER1_CC1_PA6   SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
1266 #define TIMER1_CC1_PA7   SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
1267 #define TIMER1_CC1_PA8   SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
1268 #define TIMER1_CC1_PB0   SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
1269 #define TIMER1_CC1_PB1   SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
1270 #define TIMER1_CC1_PB2   SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
1271 #define TIMER1_CC1_PB3   SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
1272 #define TIMER1_CC1_PB4   SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
1273 #define TIMER1_CC1_PC0   SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
1274 #define TIMER1_CC1_PC1   SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
1275 #define TIMER1_CC1_PC2   SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
1276 #define TIMER1_CC1_PC3   SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
1277 #define TIMER1_CC1_PC4   SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
1278 #define TIMER1_CC1_PC5   SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
1279 #define TIMER1_CC1_PC6   SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
1280 #define TIMER1_CC1_PC7   SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
1281 #define TIMER1_CC1_PD0   SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
1282 #define TIMER1_CC1_PD1   SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
1283 #define TIMER1_CC1_PD2   SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
1284 #define TIMER1_CC1_PD3   SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
1285 #define TIMER1_CC2_PA0   SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
1286 #define TIMER1_CC2_PA1   SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
1287 #define TIMER1_CC2_PA2   SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
1288 #define TIMER1_CC2_PA3   SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
1289 #define TIMER1_CC2_PA4   SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
1290 #define TIMER1_CC2_PA5   SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
1291 #define TIMER1_CC2_PA6   SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
1292 #define TIMER1_CC2_PA7   SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
1293 #define TIMER1_CC2_PA8   SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
1294 #define TIMER1_CC2_PB0   SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
1295 #define TIMER1_CC2_PB1   SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
1296 #define TIMER1_CC2_PB2   SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
1297 #define TIMER1_CC2_PB3   SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
1298 #define TIMER1_CC2_PB4   SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
1299 #define TIMER1_CC2_PC0   SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
1300 #define TIMER1_CC2_PC1   SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
1301 #define TIMER1_CC2_PC2   SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
1302 #define TIMER1_CC2_PC3   SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
1303 #define TIMER1_CC2_PC4   SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
1304 #define TIMER1_CC2_PC5   SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
1305 #define TIMER1_CC2_PC6   SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
1306 #define TIMER1_CC2_PC7   SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
1307 #define TIMER1_CC2_PD0   SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
1308 #define TIMER1_CC2_PD1   SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
1309 #define TIMER1_CC2_PD2   SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
1310 #define TIMER1_CC2_PD3   SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
1311 #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
1312 #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
1313 #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
1314 #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
1315 #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
1316 #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
1317 #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
1318 #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
1319 #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
1320 #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
1321 #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
1322 #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
1323 #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
1324 #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
1325 #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
1326 #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
1327 #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
1328 #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
1329 #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
1330 #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
1331 #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
1332 #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
1333 #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
1334 #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
1335 #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
1336 #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
1337 #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
1338 #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
1339 #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
1340 #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
1341 #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
1342 #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
1343 #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
1344 #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
1345 #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
1346 #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
1347 #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
1348 #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
1349 #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
1350 #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
1351 #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
1352 #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
1353 #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
1354 #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
1355 #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
1356 #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
1357 #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
1358 #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
1359 #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
1360 #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
1361 #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
1362 #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
1363 #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
1364 #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
1365 #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
1366 #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
1367 #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
1368 #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
1369 #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
1370 #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
1371 #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
1372 #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
1373 #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
1374 #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
1375 #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
1376 #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
1377 #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
1378 #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
1379 #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
1380 #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
1381 #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
1382 #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
1383 #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
1384 #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
1385 #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
1386 #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
1387 #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
1388 #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
1390 #define TIMER2_CC0_PA0   SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
1391 #define TIMER2_CC0_PA1   SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
1392 #define TIMER2_CC0_PA2   SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
1393 #define TIMER2_CC0_PA3   SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
1394 #define TIMER2_CC0_PA4   SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
1395 #define TIMER2_CC0_PA5   SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
1396 #define TIMER2_CC0_PA6   SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
1397 #define TIMER2_CC0_PA7   SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
1398 #define TIMER2_CC0_PA8   SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
1399 #define TIMER2_CC0_PB0   SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
1400 #define TIMER2_CC0_PB1   SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
1401 #define TIMER2_CC0_PB2   SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
1402 #define TIMER2_CC0_PB3   SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
1403 #define TIMER2_CC0_PB4   SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
1404 #define TIMER2_CC1_PA0   SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
1405 #define TIMER2_CC1_PA1   SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
1406 #define TIMER2_CC1_PA2   SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
1407 #define TIMER2_CC1_PA3   SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
1408 #define TIMER2_CC1_PA4   SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
1409 #define TIMER2_CC1_PA5   SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
1410 #define TIMER2_CC1_PA6   SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
1411 #define TIMER2_CC1_PA7   SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
1412 #define TIMER2_CC1_PA8   SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
1413 #define TIMER2_CC1_PB0   SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
1414 #define TIMER2_CC1_PB1   SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
1415 #define TIMER2_CC1_PB2   SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
1416 #define TIMER2_CC1_PB3   SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
1417 #define TIMER2_CC1_PB4   SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
1418 #define TIMER2_CC2_PA0   SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
1419 #define TIMER2_CC2_PA1   SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
1420 #define TIMER2_CC2_PA2   SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
1421 #define TIMER2_CC2_PA3   SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
1422 #define TIMER2_CC2_PA4   SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
1423 #define TIMER2_CC2_PA5   SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
1424 #define TIMER2_CC2_PA6   SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
1425 #define TIMER2_CC2_PA7   SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
1426 #define TIMER2_CC2_PA8   SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
1427 #define TIMER2_CC2_PB0   SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
1428 #define TIMER2_CC2_PB1   SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
1429 #define TIMER2_CC2_PB2   SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
1430 #define TIMER2_CC2_PB3   SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
1431 #define TIMER2_CC2_PB4   SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
1432 #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
1433 #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
1434 #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
1435 #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
1436 #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
1437 #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
1438 #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
1439 #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
1440 #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
1441 #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
1442 #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
1443 #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
1444 #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
1445 #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
1446 #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
1447 #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
1448 #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
1449 #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
1450 #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
1451 #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
1452 #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
1453 #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
1454 #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
1455 #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
1456 #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
1457 #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
1458 #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
1459 #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
1460 #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
1461 #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
1462 #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
1463 #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
1464 #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
1465 #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
1466 #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
1467 #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
1468 #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
1469 #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
1470 #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
1471 #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
1472 #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
1473 #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
1475 #define TIMER3_CC0_PC0   SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
1476 #define TIMER3_CC0_PC1   SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
1477 #define TIMER3_CC0_PC2   SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
1478 #define TIMER3_CC0_PC3   SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
1479 #define TIMER3_CC0_PC4   SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
1480 #define TIMER3_CC0_PC5   SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
1481 #define TIMER3_CC0_PC6   SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
1482 #define TIMER3_CC0_PC7   SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
1483 #define TIMER3_CC0_PD0   SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
1484 #define TIMER3_CC0_PD1   SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
1485 #define TIMER3_CC0_PD2   SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
1486 #define TIMER3_CC0_PD3   SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
1487 #define TIMER3_CC1_PC0   SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
1488 #define TIMER3_CC1_PC1   SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
1489 #define TIMER3_CC1_PC2   SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
1490 #define TIMER3_CC1_PC3   SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
1491 #define TIMER3_CC1_PC4   SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
1492 #define TIMER3_CC1_PC5   SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
1493 #define TIMER3_CC1_PC6   SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
1494 #define TIMER3_CC1_PC7   SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
1495 #define TIMER3_CC1_PD0   SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
1496 #define TIMER3_CC1_PD1   SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
1497 #define TIMER3_CC1_PD2   SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
1498 #define TIMER3_CC1_PD3   SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
1499 #define TIMER3_CC2_PC0   SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
1500 #define TIMER3_CC2_PC1   SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
1501 #define TIMER3_CC2_PC2   SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
1502 #define TIMER3_CC2_PC3   SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
1503 #define TIMER3_CC2_PC4   SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
1504 #define TIMER3_CC2_PC5   SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
1505 #define TIMER3_CC2_PC6   SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
1506 #define TIMER3_CC2_PC7   SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
1507 #define TIMER3_CC2_PD0   SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
1508 #define TIMER3_CC2_PD1   SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
1509 #define TIMER3_CC2_PD2   SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
1510 #define TIMER3_CC2_PD3   SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
1511 #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
1512 #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
1513 #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
1514 #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
1515 #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
1516 #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
1517 #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
1518 #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
1519 #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
1520 #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
1521 #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
1522 #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
1523 #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
1524 #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
1525 #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
1526 #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
1527 #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
1528 #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
1529 #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
1530 #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
1531 #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
1532 #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
1533 #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
1534 #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
1535 #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
1536 #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
1537 #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
1538 #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
1539 #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
1540 #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
1541 #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
1542 #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
1543 #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
1544 #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
1545 #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
1546 #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
1548 #define TIMER4_CC0_PA0   SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
1549 #define TIMER4_CC0_PA1   SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
1550 #define TIMER4_CC0_PA2   SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
1551 #define TIMER4_CC0_PA3   SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
1552 #define TIMER4_CC0_PA4   SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
1553 #define TIMER4_CC0_PA5   SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
1554 #define TIMER4_CC0_PA6   SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
1555 #define TIMER4_CC0_PA7   SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
1556 #define TIMER4_CC0_PA8   SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
1557 #define TIMER4_CC0_PB0   SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
1558 #define TIMER4_CC0_PB1   SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
1559 #define TIMER4_CC0_PB2   SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
1560 #define TIMER4_CC0_PB3   SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
1561 #define TIMER4_CC0_PB4   SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
1562 #define TIMER4_CC1_PA0   SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
1563 #define TIMER4_CC1_PA1   SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
1564 #define TIMER4_CC1_PA2   SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
1565 #define TIMER4_CC1_PA3   SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
1566 #define TIMER4_CC1_PA4   SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
1567 #define TIMER4_CC1_PA5   SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
1568 #define TIMER4_CC1_PA6   SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
1569 #define TIMER4_CC1_PA7   SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
1570 #define TIMER4_CC1_PA8   SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
1571 #define TIMER4_CC1_PB0   SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
1572 #define TIMER4_CC1_PB1   SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
1573 #define TIMER4_CC1_PB2   SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
1574 #define TIMER4_CC1_PB3   SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
1575 #define TIMER4_CC1_PB4   SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
1576 #define TIMER4_CC2_PA0   SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
1577 #define TIMER4_CC2_PA1   SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
1578 #define TIMER4_CC2_PA2   SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
1579 #define TIMER4_CC2_PA3   SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
1580 #define TIMER4_CC2_PA4   SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
1581 #define TIMER4_CC2_PA5   SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
1582 #define TIMER4_CC2_PA6   SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
1583 #define TIMER4_CC2_PA7   SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
1584 #define TIMER4_CC2_PA8   SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
1585 #define TIMER4_CC2_PB0   SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
1586 #define TIMER4_CC2_PB1   SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
1587 #define TIMER4_CC2_PB2   SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
1588 #define TIMER4_CC2_PB3   SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
1589 #define TIMER4_CC2_PB4   SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
1590 #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
1591 #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
1592 #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
1593 #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
1594 #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
1595 #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
1596 #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
1597 #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
1598 #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
1599 #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
1600 #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
1601 #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
1602 #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
1603 #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
1604 #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
1605 #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
1606 #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
1607 #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
1608 #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
1609 #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
1610 #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
1611 #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
1612 #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
1613 #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
1614 #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
1615 #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
1616 #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
1617 #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
1618 #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
1619 #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
1620 #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
1621 #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
1622 #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
1623 #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
1624 #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
1625 #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
1626 #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
1627 #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
1628 #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
1629 #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
1630 #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
1631 #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
1633 #define USART0_CS_PA0  SILABS_DBUS_USART0_CS(0x0, 0x0)
1634 #define USART0_CS_PA1  SILABS_DBUS_USART0_CS(0x0, 0x1)
1635 #define USART0_CS_PA2  SILABS_DBUS_USART0_CS(0x0, 0x2)
1636 #define USART0_CS_PA3  SILABS_DBUS_USART0_CS(0x0, 0x3)
1637 #define USART0_CS_PA4  SILABS_DBUS_USART0_CS(0x0, 0x4)
1638 #define USART0_CS_PA5  SILABS_DBUS_USART0_CS(0x0, 0x5)
1639 #define USART0_CS_PA6  SILABS_DBUS_USART0_CS(0x0, 0x6)
1640 #define USART0_CS_PA7  SILABS_DBUS_USART0_CS(0x0, 0x7)
1641 #define USART0_CS_PA8  SILABS_DBUS_USART0_CS(0x0, 0x8)
1642 #define USART0_CS_PB0  SILABS_DBUS_USART0_CS(0x1, 0x0)
1643 #define USART0_CS_PB1  SILABS_DBUS_USART0_CS(0x1, 0x1)
1644 #define USART0_CS_PB2  SILABS_DBUS_USART0_CS(0x1, 0x2)
1645 #define USART0_CS_PB3  SILABS_DBUS_USART0_CS(0x1, 0x3)
1646 #define USART0_CS_PB4  SILABS_DBUS_USART0_CS(0x1, 0x4)
1647 #define USART0_CS_PC0  SILABS_DBUS_USART0_CS(0x2, 0x0)
1648 #define USART0_CS_PC1  SILABS_DBUS_USART0_CS(0x2, 0x1)
1649 #define USART0_CS_PC2  SILABS_DBUS_USART0_CS(0x2, 0x2)
1650 #define USART0_CS_PC3  SILABS_DBUS_USART0_CS(0x2, 0x3)
1651 #define USART0_CS_PC4  SILABS_DBUS_USART0_CS(0x2, 0x4)
1652 #define USART0_CS_PC5  SILABS_DBUS_USART0_CS(0x2, 0x5)
1653 #define USART0_CS_PC6  SILABS_DBUS_USART0_CS(0x2, 0x6)
1654 #define USART0_CS_PC7  SILABS_DBUS_USART0_CS(0x2, 0x7)
1655 #define USART0_CS_PD0  SILABS_DBUS_USART0_CS(0x3, 0x0)
1656 #define USART0_CS_PD1  SILABS_DBUS_USART0_CS(0x3, 0x1)
1657 #define USART0_CS_PD2  SILABS_DBUS_USART0_CS(0x3, 0x2)
1658 #define USART0_CS_PD3  SILABS_DBUS_USART0_CS(0x3, 0x3)
1659 #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
1660 #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
1661 #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
1662 #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
1663 #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
1664 #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
1665 #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
1666 #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
1667 #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
1668 #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
1669 #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
1670 #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
1671 #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
1672 #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
1673 #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
1674 #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
1675 #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
1676 #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
1677 #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
1678 #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
1679 #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
1680 #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
1681 #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
1682 #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
1683 #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
1684 #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
1685 #define USART0_RX_PA0  SILABS_DBUS_USART0_RX(0x0, 0x0)
1686 #define USART0_RX_PA1  SILABS_DBUS_USART0_RX(0x0, 0x1)
1687 #define USART0_RX_PA2  SILABS_DBUS_USART0_RX(0x0, 0x2)
1688 #define USART0_RX_PA3  SILABS_DBUS_USART0_RX(0x0, 0x3)
1689 #define USART0_RX_PA4  SILABS_DBUS_USART0_RX(0x0, 0x4)
1690 #define USART0_RX_PA5  SILABS_DBUS_USART0_RX(0x0, 0x5)
1691 #define USART0_RX_PA6  SILABS_DBUS_USART0_RX(0x0, 0x6)
1692 #define USART0_RX_PA7  SILABS_DBUS_USART0_RX(0x0, 0x7)
1693 #define USART0_RX_PA8  SILABS_DBUS_USART0_RX(0x0, 0x8)
1694 #define USART0_RX_PB0  SILABS_DBUS_USART0_RX(0x1, 0x0)
1695 #define USART0_RX_PB1  SILABS_DBUS_USART0_RX(0x1, 0x1)
1696 #define USART0_RX_PB2  SILABS_DBUS_USART0_RX(0x1, 0x2)
1697 #define USART0_RX_PB3  SILABS_DBUS_USART0_RX(0x1, 0x3)
1698 #define USART0_RX_PB4  SILABS_DBUS_USART0_RX(0x1, 0x4)
1699 #define USART0_RX_PC0  SILABS_DBUS_USART0_RX(0x2, 0x0)
1700 #define USART0_RX_PC1  SILABS_DBUS_USART0_RX(0x2, 0x1)
1701 #define USART0_RX_PC2  SILABS_DBUS_USART0_RX(0x2, 0x2)
1702 #define USART0_RX_PC3  SILABS_DBUS_USART0_RX(0x2, 0x3)
1703 #define USART0_RX_PC4  SILABS_DBUS_USART0_RX(0x2, 0x4)
1704 #define USART0_RX_PC5  SILABS_DBUS_USART0_RX(0x2, 0x5)
1705 #define USART0_RX_PC6  SILABS_DBUS_USART0_RX(0x2, 0x6)
1706 #define USART0_RX_PC7  SILABS_DBUS_USART0_RX(0x2, 0x7)
1707 #define USART0_RX_PD0  SILABS_DBUS_USART0_RX(0x3, 0x0)
1708 #define USART0_RX_PD1  SILABS_DBUS_USART0_RX(0x3, 0x1)
1709 #define USART0_RX_PD2  SILABS_DBUS_USART0_RX(0x3, 0x2)
1710 #define USART0_RX_PD3  SILABS_DBUS_USART0_RX(0x3, 0x3)
1711 #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
1712 #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
1713 #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
1714 #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
1715 #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
1716 #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
1717 #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1718 #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
1719 #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
1720 #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
1721 #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
1722 #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
1723 #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
1724 #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
1725 #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
1726 #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1727 #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
1728 #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1729 #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
1730 #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1731 #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
1732 #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
1733 #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
1734 #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1735 #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1736 #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
1737 #define USART0_TX_PA0  SILABS_DBUS_USART0_TX(0x0, 0x0)
1738 #define USART0_TX_PA1  SILABS_DBUS_USART0_TX(0x0, 0x1)
1739 #define USART0_TX_PA2  SILABS_DBUS_USART0_TX(0x0, 0x2)
1740 #define USART0_TX_PA3  SILABS_DBUS_USART0_TX(0x0, 0x3)
1741 #define USART0_TX_PA4  SILABS_DBUS_USART0_TX(0x0, 0x4)
1742 #define USART0_TX_PA5  SILABS_DBUS_USART0_TX(0x0, 0x5)
1743 #define USART0_TX_PA6  SILABS_DBUS_USART0_TX(0x0, 0x6)
1744 #define USART0_TX_PA7  SILABS_DBUS_USART0_TX(0x0, 0x7)
1745 #define USART0_TX_PA8  SILABS_DBUS_USART0_TX(0x0, 0x8)
1746 #define USART0_TX_PB0  SILABS_DBUS_USART0_TX(0x1, 0x0)
1747 #define USART0_TX_PB1  SILABS_DBUS_USART0_TX(0x1, 0x1)
1748 #define USART0_TX_PB2  SILABS_DBUS_USART0_TX(0x1, 0x2)
1749 #define USART0_TX_PB3  SILABS_DBUS_USART0_TX(0x1, 0x3)
1750 #define USART0_TX_PB4  SILABS_DBUS_USART0_TX(0x1, 0x4)
1751 #define USART0_TX_PC0  SILABS_DBUS_USART0_TX(0x2, 0x0)
1752 #define USART0_TX_PC1  SILABS_DBUS_USART0_TX(0x2, 0x1)
1753 #define USART0_TX_PC2  SILABS_DBUS_USART0_TX(0x2, 0x2)
1754 #define USART0_TX_PC3  SILABS_DBUS_USART0_TX(0x2, 0x3)
1755 #define USART0_TX_PC4  SILABS_DBUS_USART0_TX(0x2, 0x4)
1756 #define USART0_TX_PC5  SILABS_DBUS_USART0_TX(0x2, 0x5)
1757 #define USART0_TX_PC6  SILABS_DBUS_USART0_TX(0x2, 0x6)
1758 #define USART0_TX_PC7  SILABS_DBUS_USART0_TX(0x2, 0x7)
1759 #define USART0_TX_PD0  SILABS_DBUS_USART0_TX(0x3, 0x0)
1760 #define USART0_TX_PD1  SILABS_DBUS_USART0_TX(0x3, 0x1)
1761 #define USART0_TX_PD2  SILABS_DBUS_USART0_TX(0x3, 0x2)
1762 #define USART0_TX_PD3  SILABS_DBUS_USART0_TX(0x3, 0x3)
1763 #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
1764 #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
1765 #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
1766 #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
1767 #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
1768 #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
1769 #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1770 #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
1771 #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
1772 #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
1773 #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
1774 #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
1775 #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
1776 #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
1777 #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
1778 #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1779 #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
1780 #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1781 #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
1782 #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1783 #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
1784 #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
1785 #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
1786 #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1787 #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1788 #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
1790 #define USART1_CS_PA0  SILABS_DBUS_USART1_CS(0x0, 0x0)
1791 #define USART1_CS_PA1  SILABS_DBUS_USART1_CS(0x0, 0x1)
1792 #define USART1_CS_PA2  SILABS_DBUS_USART1_CS(0x0, 0x2)
1793 #define USART1_CS_PA3  SILABS_DBUS_USART1_CS(0x0, 0x3)
1794 #define USART1_CS_PA4  SILABS_DBUS_USART1_CS(0x0, 0x4)
1795 #define USART1_CS_PA5  SILABS_DBUS_USART1_CS(0x0, 0x5)
1796 #define USART1_CS_PA6  SILABS_DBUS_USART1_CS(0x0, 0x6)
1797 #define USART1_CS_PA7  SILABS_DBUS_USART1_CS(0x0, 0x7)
1798 #define USART1_CS_PA8  SILABS_DBUS_USART1_CS(0x0, 0x8)
1799 #define USART1_CS_PB0  SILABS_DBUS_USART1_CS(0x1, 0x0)
1800 #define USART1_CS_PB1  SILABS_DBUS_USART1_CS(0x1, 0x1)
1801 #define USART1_CS_PB2  SILABS_DBUS_USART1_CS(0x1, 0x2)
1802 #define USART1_CS_PB3  SILABS_DBUS_USART1_CS(0x1, 0x3)
1803 #define USART1_CS_PB4  SILABS_DBUS_USART1_CS(0x1, 0x4)
1804 #define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
1805 #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
1806 #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
1807 #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
1808 #define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
1809 #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
1810 #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1811 #define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7)
1812 #define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
1813 #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
1814 #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
1815 #define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
1816 #define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
1817 #define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
1818 #define USART1_RX_PA0  SILABS_DBUS_USART1_RX(0x0, 0x0)
1819 #define USART1_RX_PA1  SILABS_DBUS_USART1_RX(0x0, 0x1)
1820 #define USART1_RX_PA2  SILABS_DBUS_USART1_RX(0x0, 0x2)
1821 #define USART1_RX_PA3  SILABS_DBUS_USART1_RX(0x0, 0x3)
1822 #define USART1_RX_PA4  SILABS_DBUS_USART1_RX(0x0, 0x4)
1823 #define USART1_RX_PA5  SILABS_DBUS_USART1_RX(0x0, 0x5)
1824 #define USART1_RX_PA6  SILABS_DBUS_USART1_RX(0x0, 0x6)
1825 #define USART1_RX_PA7  SILABS_DBUS_USART1_RX(0x0, 0x7)
1826 #define USART1_RX_PA8  SILABS_DBUS_USART1_RX(0x0, 0x8)
1827 #define USART1_RX_PB0  SILABS_DBUS_USART1_RX(0x1, 0x0)
1828 #define USART1_RX_PB1  SILABS_DBUS_USART1_RX(0x1, 0x1)
1829 #define USART1_RX_PB2  SILABS_DBUS_USART1_RX(0x1, 0x2)
1830 #define USART1_RX_PB3  SILABS_DBUS_USART1_RX(0x1, 0x3)
1831 #define USART1_RX_PB4  SILABS_DBUS_USART1_RX(0x1, 0x4)
1832 #define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
1833 #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
1834 #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
1835 #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
1836 #define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
1837 #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
1838 #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
1839 #define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7)
1840 #define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
1841 #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
1842 #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
1843 #define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
1844 #define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
1845 #define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
1846 #define USART1_TX_PA0  SILABS_DBUS_USART1_TX(0x0, 0x0)
1847 #define USART1_TX_PA1  SILABS_DBUS_USART1_TX(0x0, 0x1)
1848 #define USART1_TX_PA2  SILABS_DBUS_USART1_TX(0x0, 0x2)
1849 #define USART1_TX_PA3  SILABS_DBUS_USART1_TX(0x0, 0x3)
1850 #define USART1_TX_PA4  SILABS_DBUS_USART1_TX(0x0, 0x4)
1851 #define USART1_TX_PA5  SILABS_DBUS_USART1_TX(0x0, 0x5)
1852 #define USART1_TX_PA6  SILABS_DBUS_USART1_TX(0x0, 0x6)
1853 #define USART1_TX_PA7  SILABS_DBUS_USART1_TX(0x0, 0x7)
1854 #define USART1_TX_PA8  SILABS_DBUS_USART1_TX(0x0, 0x8)
1855 #define USART1_TX_PB0  SILABS_DBUS_USART1_TX(0x1, 0x0)
1856 #define USART1_TX_PB1  SILABS_DBUS_USART1_TX(0x1, 0x1)
1857 #define USART1_TX_PB2  SILABS_DBUS_USART1_TX(0x1, 0x2)
1858 #define USART1_TX_PB3  SILABS_DBUS_USART1_TX(0x1, 0x3)
1859 #define USART1_TX_PB4  SILABS_DBUS_USART1_TX(0x1, 0x4)
1860 #define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
1861 #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
1862 #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
1863 #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
1864 #define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
1865 #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
1866 #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
1867 #define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7)
1868 #define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)
1869 #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
1870 #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
1871 #define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
1872 #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
1873 #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)