Lines Matching +full:0 +full:x2

12     1. channel: the dma stream from 0 to <dma-requests>
14     this value is 0 for Memory-to-memory transfers
20                0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
21                0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
22                0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
23                0x3: reserved for PERIPH to PERIPH
25                0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
26                0x1: STM32_DMA_PERIPH_INC: increment address between transfers
28                0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
29                0x1: STM32_DMA_MEM_INC: increment address between transfers
31                0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
32                0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
33                0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
34                0x3: reserved
36                0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
37                0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
38                0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
39                0x3: reserved
41                0x0: STM32_DMA_OFFSET_LINKED_BUS: offset size is linked to the peripheral bus width
42                0x1: STM32_DMA_OFFSET_FIXED_4: offset size is fixed to 4 (32-bit alignment)
44                0x0: STM32_DMA_PRIORITY_LOW: low
45                0x1: STM32_DMA_PRIORITY_MEDIUM: medium
46                0x2: hSTM32_DMA_PRIORITY_HIGH: high
47                0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high
49         -bit 0-1: DMA FIFO threshold selection
50                0x0: STM32_DMA_FIFO_1_4: 1/4 full FIFO
51                0x1: STM32_DMA_FIFO_HALF: 1/2 full FIFO
52                0x2: STM32_DMA_FIFO_3_4: 3/4 full FIFO
53                0x3: STM32_DMA_FIFO_FULL: full FIFO
70     Rx using stream 2 on channel 3 (stream 0 on channel 3 is also possible)