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Searched refs:I915_WRITE (Results 1 – 25 of 55) sorted by relevance

123

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_color.c116 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); in ilk_load_ycbcr_conversion_matrix()
117 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); in ilk_load_ycbcr_conversion_matrix()
118 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); in ilk_load_ycbcr_conversion_matrix()
120 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU); in ilk_load_ycbcr_conversion_matrix()
121 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU); in ilk_load_ycbcr_conversion_matrix()
123 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY); in ilk_load_ycbcr_conversion_matrix()
124 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY); in ilk_load_ycbcr_conversion_matrix()
126 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV); in ilk_load_ycbcr_conversion_matrix()
127 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV); in ilk_load_ycbcr_conversion_matrix()
129 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI); in ilk_load_ycbcr_conversion_matrix()
[all …]
Dintel_workarounds.c594 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, in gen9_gt_workarounds_apply()
598 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | in gen9_gt_workarounds_apply()
603 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in gen9_gt_workarounds_apply()
612 I915_WRITE(MMCD_MISC_CTRL, in gen9_gt_workarounds_apply()
619 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in gen9_gt_workarounds_apply()
628 I915_WRITE(GEN8_L3SQCREG1, val); in gen9_gt_workarounds_apply()
632 I915_WRITE(GEN8_L3SQCREG4, in gen9_gt_workarounds_apply()
636 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, in gen9_gt_workarounds_apply()
645 I915_WRITE(GEN8_GARBCNTL, in skl_gt_workarounds_apply()
649 I915_WRITE(GEN7_UCGCTL4, in skl_gt_workarounds_apply()
[all …]
Dvlv_dsi.c100 I915_WRITE(reg, val); in write_data()
163 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); in intel_dsi_host_transfer()
173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); in intel_dsi_host_transfer()
262 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
268 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
374 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
380 I915_WRITE(MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
389 I915_WRITE(MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
426 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
434 I915_WRITE(MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
[all …]
Di915_suspend.c47 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
54 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); in i915_restore_display()
118 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | in i915_restore_state()
122 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); in i915_restore_state()
127 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); in i915_restore_state()
128 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); in i915_restore_state()
131 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); in i915_restore_state()
134 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); in i915_restore_state()
137 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); in i915_restore_state()
138 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); in i915_restore_state()
[all …]
Dintel_pm.c66 I915_WRITE(CHICKEN_PAR1_1, in gen9_init_clock_gating()
72 I915_WRITE(CHICKEN_PAR1_1, in gen9_init_clock_gating()
76 I915_WRITE(GEN8_CHICKEN_DCPR_1, in gen9_init_clock_gating()
81 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
86 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
91 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
101 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
108 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
115 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
128 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
[all …]
Dintel_guc_fw.c105 I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES | in guc_prepare_xfer()
113 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
115 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
119 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | in guc_prepare_xfer()
123 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF); in guc_prepare_xfer()
141 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); in guc_xfer_rsa()
165 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size); in guc_xfer_ucode()
169 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); in guc_xfer_ucode()
170 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); in guc_xfer_ucode()
176 I915_WRITE(DMA_ADDR_1_LOW, 0x2000); in guc_xfer_ucode()
[all …]
Dintel_hdcp.c79 I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); in intel_hdcp_clear_keys()
80 I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | in intel_hdcp_clear_keys()
118 I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); in intel_hdcp_load_keys()
131 I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); in intel_hdcp_load_keys()
139 I915_WRITE(HDCP_SHA_TEXT, sha_text); in intel_write_sha_text()
198 I915_WRITE(HDCP_SHA_V_PRIME(i), vprime); in intel_hdcp_validate_v_prime()
215 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
232 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
264 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); in intel_hdcp_validate_v_prime()
272 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); in intel_hdcp_validate_v_prime()
[all …]
Di915_irq.c136 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
138 I915_WRITE(GEN8_##type##_IER(which), 0); \
139 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
141 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
146 I915_WRITE(type##IMR, 0xffffffff); \
148 I915_WRITE(type##IER, 0); \
149 I915_WRITE(type##IIR, 0xffffffff); \
151 I915_WRITE(type##IIR, 0xffffffff); \
178 I915_WRITE(reg, 0xffffffff); in gen3_assert_iir_is_zero()
180 I915_WRITE(reg, 0xffffffff); in gen3_assert_iir_is_zero()
[all …]
Dintel_tv.c821 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
832 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
950 I915_WRITE(TV_H_CTL_1, hctl1); in set_tv_mode_timings()
951 I915_WRITE(TV_H_CTL_2, hctl2); in set_tv_mode_timings()
952 I915_WRITE(TV_H_CTL_3, hctl3); in set_tv_mode_timings()
953 I915_WRITE(TV_V_CTL_1, vctl1); in set_tv_mode_timings()
954 I915_WRITE(TV_V_CTL_2, vctl2); in set_tv_mode_timings()
955 I915_WRITE(TV_V_CTL_3, vctl3); in set_tv_mode_timings()
956 I915_WRITE(TV_V_CTL_4, vctl4); in set_tv_mode_timings()
957 I915_WRITE(TV_V_CTL_5, vctl5); in set_tv_mode_timings()
[all …]
Dintel_huc_fw.c123 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); in huc_fw_xfer()
124 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); in huc_fw_xfer()
129 I915_WRITE(DMA_ADDR_1_LOW, 0); in huc_fw_xfer()
130 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); in huc_fw_xfer()
133 I915_WRITE(DMA_COPY_SIZE, size); in huc_fw_xfer()
136 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA)); in huc_fw_xfer()
144 I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL)); in huc_fw_xfer()
Dintel_fbc.c106 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
137 I915_WRITE(FBC_TAG(i), 0); in i8xx_fbc_activate()
145 I915_WRITE(FBC_CONTROL2, fbc_ctl2); in i8xx_fbc_activate()
146 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); in i8xx_fbc_activate()
157 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_activate()
178 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); in g4x_fbc_activate()
180 I915_WRITE(DPFC_FENCE_YOFF, 0); in g4x_fbc_activate()
184 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in g4x_fbc_activate()
195 I915_WRITE(DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
207 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); in intel_fbc_recompress()
[all …]
Dintel_audio.c228 I915_WRITE(reg_elda, tmp); in intel_eld_uptodate()
255 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_disable()
286 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
291 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i)); in g4x_audio_codec_enable()
295 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
330 I915_WRITE(HSW_AUD_CFG(pipe), tmp); in hsw_dp_audio_config_update()
343 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); in hsw_dp_audio_config_update()
377 I915_WRITE(HSW_AUD_CFG(pipe), tmp); in hsw_hdmi_audio_config_update()
386 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); in hsw_hdmi_audio_config_update()
420 I915_WRITE(HSW_AUD_CFG(pipe), tmp); in hsw_audio_codec_disable()
[all …]
Dintel_ddi.c987 I915_WRITE(DDI_BUF_TRANS_LO(port, i), in intel_prepare_dp_ddi_buffers()
989 I915_WRITE(DDI_BUF_TRANS_HI(port, i), in intel_prepare_dp_ddi_buffers()
1021 I915_WRITE(DDI_BUF_TRANS_LO(port, 9), in intel_prepare_hdmi_ddi_buffers()
1023 I915_WRITE(DDI_BUF_TRANS_HI(port, 9), in intel_prepare_hdmi_ddi_buffers()
1127 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
1135 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1141 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1145 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); in hsw_fdi_link_train()
1152 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
1162 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
[all …]
Dintel_sideband.c62 I915_WRITE(VLV_IOSF_ADDR, addr); in vlv_sideband_rw()
63 I915_WRITE(VLV_IOSF_DATA, is_read ? 0 : *val); in vlv_sideband_rw()
64 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); in vlv_sideband_rw()
218 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_read()
219 I915_WRITE(SBI_DATA, 0); in intel_sbi_read()
225 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); in intel_sbi_read()
258 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_write()
259 I915_WRITE(SBI_DATA, value); in intel_sbi_write()
265 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); in intel_sbi_write()
Di915_drv.c1237 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); in i915_driver_register()
2334 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); in vlv_restore_gunit_s0ix_state()
2335 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); in vlv_restore_gunit_s0ix_state()
2336 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); in vlv_restore_gunit_s0ix_state()
2337 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); in vlv_restore_gunit_s0ix_state()
2338 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); in vlv_restore_gunit_s0ix_state()
2341 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); in vlv_restore_gunit_s0ix_state()
2343 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); in vlv_restore_gunit_s0ix_state()
2344 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); in vlv_restore_gunit_s0ix_state()
2346 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); in vlv_restore_gunit_s0ix_state()
[all …]
Dintel_panel.c536 I915_WRITE(BLC_PWM_PCH_CTL2, val | level); in lpt_set_backlight()
546 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
574 I915_WRITE(BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
585 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
594 I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level); in bxt_set_backlight()
675 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in lpt_disable_backlight()
679 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in lpt_disable_backlight()
691 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in pch_disable_backlight()
694 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in pch_disable_backlight()
710 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
[all …]
Dintel_hdmi.c169 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
173 I915_WRITE(VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
178 I915_WRITE(VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
185 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
226 I915_WRITE(reg, val); in ibx_write_infoframe()
230 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
235 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
242 I915_WRITE(reg, val); in ibx_write_infoframe()
289 I915_WRITE(reg, val); in cpt_write_infoframe()
293 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
[all …]
Dintel_dpll_mgr.c367 I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_prepare()
368 I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_prepare()
392 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
403 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
421 I915_WRITE(PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
480 I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
488 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
500 I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); in hsw_ddi_wrpll_disable()
510 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_ddi_spll_disable()
940 I915_WRITE(DPLL_CTRL1, val); in skl_ddi_pll_write_ctrl1()
[all …]
Dicl_dsi.c45 I915_WRITE(ICL_DSI_ESC_CLK_DIV(port), in gen11_dsi_program_esc_clk_div()
51 I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port), in gen11_dsi_program_esc_clk_div()
67 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); in gen11_dsi_enable_io_power()
104 I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask); in gen11_dsi_power_up_lanes()
Dvlv_dsi_pll.c241 I915_WRITE(BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_disable()
368 I915_WRITE(MIPI_CTRL(port), temp | in vlv_dsi_reset_clocks()
416 I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK); in glk_dsi_program_esc_clock()
417 I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK); in glk_dsi_program_esc_clock()
471 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
533 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
547 I915_WRITE(BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_enable()
575 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
579 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp); in bxt_dsi_reset_clocks()
583 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp); in bxt_dsi_reset_clocks()
[all …]
Dintel_pipe_crc.c184 I915_WRITE(PORT_DFT2_G4X, tmp); in vlv_pipe_crc_ctl_reg()
251 I915_WRITE(PORT_DFT_I9XX, in i9xx_pipe_crc_ctl_reg()
259 I915_WRITE(PORT_DFT2_G4X, tmp); in i9xx_pipe_crc_ctl_reg()
285 I915_WRITE(PORT_DFT2_G4X, tmp); in vlv_undo_pipe_scramble_reset()
298 I915_WRITE(PORT_DFT2_G4X, tmp); in g4x_undo_pipe_scramble_reset()
301 I915_WRITE(PORT_DFT_I9XX, in g4x_undo_pipe_scramble_reset()
497 I915_WRITE(PIPE_CRC_CTL(crtc->index), val); in intel_crtc_set_crc_source()
535 I915_WRITE(PIPE_CRC_CTL(crtc->index), val); in intel_crtc_enable_pipe_crc()
550 I915_WRITE(PIPE_CRC_CTL(crtc->index), 0); in intel_crtc_disable_pipe_crc()
Dintel_crt.c178 I915_WRITE(BCLRPAT(crtc->pipe), 0); in intel_crt_set_dpms()
195 I915_WRITE(crt->adpa_reg, adpa); in intel_crt_set_dpms()
431 I915_WRITE(crt->adpa_reg, adpa); in intel_ironlake_crt_detect_hotplug()
440 I915_WRITE(crt->adpa_reg, save_adpa); in intel_ironlake_crt_detect_hotplug()
485 I915_WRITE(crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
492 I915_WRITE(crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
551 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
664 I915_WRITE(bclrpat_reg, 0x500050); in intel_crt_load_detect()
668 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); in intel_crt_load_detect()
678 I915_WRITE(pipeconf_reg, pipeconf); in intel_crt_load_detect()
[all …]
Dintel_runtime_pm.c409 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); in hsw_power_well_enable()
418 I915_WRITE(CNL_AUX_ANAOVRD1(id), val); in hsw_power_well_enable()
437 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), in hsw_power_well_disable()
453 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); in icl_combo_phy_aux_power_well_enable()
456 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); in icl_combo_phy_aux_power_well_enable()
470 I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX); in icl_combo_phy_aux_power_well_disable()
473 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), in icl_combo_phy_aux_power_well_disable()
539 I915_WRITE(DC_STATE_EN, state); in gen9_write_dc_state()
550 I915_WRITE(DC_STATE_EN, state); in gen9_write_dc_state()
693 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | in gen9_enable_dc5()
[all …]
Dintel_psr.c84 I915_WRITE(EDP_PSR_IMR, ~mask); in intel_psr_irq_control()
156 I915_WRITE(PSR_EVENT(cpu_transcoder), val); in intel_psr_irq_handler()
296 I915_WRITE(EDP_PSR_AUX_DATA(i >> 2), in hsw_psr_setup_aux()
307 I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl); in hsw_psr_setup_aux()
387 I915_WRITE(EDP_PSR_CTL, val); in hsw_activate_psr1()
424 I915_WRITE(EDP_PSR2_CTL, val); in hsw_activate_psr2()
567 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); in intel_psr_enable_source()
569 I915_WRITE(EDP_PSR_DEBUG, in intel_psr_enable_source()
583 I915_WRITE(EDP_PSR_DEBUG, in intel_psr_enable_source()
648 I915_WRITE(EDP_PSR2_CTL, in intel_psr_disable_source()
[all …]
Dintel_dpio_phy.c279 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
284 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
294 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
299 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
303 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
376 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()
396 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); in _bxt_ddi_phy_init()
401 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); in _bxt_ddi_phy_init()
407 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); in _bxt_ddi_phy_init()
412 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); in _bxt_ddi_phy_init()
[all …]

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