409 	I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));  in hsw_power_well_enable()
418 		I915_WRITE(CNL_AUX_ANAOVRD1(id), val);  in hsw_power_well_enable()
437 	I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),  in hsw_power_well_disable()
453 	I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));  in icl_combo_phy_aux_power_well_enable()
456 	I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);  in icl_combo_phy_aux_power_well_enable()
470 	I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);  in icl_combo_phy_aux_power_well_disable()
473 	I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),  in icl_combo_phy_aux_power_well_disable()
539 	I915_WRITE(DC_STATE_EN, state);  in gen9_write_dc_state()
550 			I915_WRITE(DC_STATE_EN, state);  in gen9_write_dc_state()
693 		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in gen9_enable_dc5()
717 		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in skl_enable_dc6()
735 			I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask);  in hsw_power_well_sync_hw()
736 		I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask);  in hsw_power_well_sync_hw()
966 	I915_WRITE(DSPCLK_GATE_D, val);  in vlv_init_display_clock_gating()
971 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);  in vlv_init_display_clock_gating()
972 	I915_WRITE(CBR1_VLV, 0);  in vlv_init_display_clock_gating()
976 	I915_WRITE(RAWCLK_FREQ_VLV,  in vlv_init_display_clock_gating()
1000 		I915_WRITE(DPLL(pipe), val);  in vlv_display_power_well_init()
1086 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);  in vlv_dpio_cmn_power_well_enable()
1100 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);  in vlv_dpio_cmn_power_well_disable()
1291 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_enable()
1317 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_dpio_cmn_power_well_disable()
1410 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_powergate_ch()
1441 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_powergate_lanes()
2954 	I915_WRITE(reg, val);  in intel_dbuf_slice_set()
3011 	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);  in icl_dbuf_enable()
3012 	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);  in icl_dbuf_enable()
3026 	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);  in icl_dbuf_disable()
3027 	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);  in icl_dbuf_disable()
3048 	I915_WRITE(MBUS_ABOX_CTL, val);  in icl_mbus_init()
3062 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);  in skl_display_core_init()
3130 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);  in bxt_display_core_init()
3236 	I915_WRITE(ICL_PORT_COMP_DW1(port), val);  in cnl_set_procmon_ref_values()
3238 	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);  in cnl_set_procmon_ref_values()
3239 	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);  in cnl_set_procmon_ref_values()
3253 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);  in cnl_display_core_init()
3258 	I915_WRITE(CHICKEN_MISC_2, val);  in cnl_display_core_init()
3265 	I915_WRITE(CNL_PORT_COMP_DW0, val);  in cnl_display_core_init()
3270 	I915_WRITE(CNL_PORT_CL1CM_DW5, val);  in cnl_display_core_init()
3322 	I915_WRITE(CHICKEN_MISC_2, val);  in cnl_display_core_uninit()
3338 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);  in icl_display_core_init()
3344 		I915_WRITE(ICL_PHY_MISC(port), val);  in icl_display_core_init()
3350 		I915_WRITE(ICL_PORT_COMP_DW0(port), val);  in icl_display_core_init()
3355 		I915_WRITE(ICL_PORT_CL_DW5(port), val);  in icl_display_core_init()
3377 	I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in icl_display_core_init()
3412 		I915_WRITE(ICL_PHY_MISC(port), val);  in icl_display_core_uninit()
3497 	I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);  in chv_phy_control_init()