Lines Matching refs:I915_WRITE
66 I915_WRITE(CHICKEN_PAR1_1, in gen9_init_clock_gating()
72 I915_WRITE(CHICKEN_PAR1_1, in gen9_init_clock_gating()
76 I915_WRITE(GEN8_CHICKEN_DCPR_1, in gen9_init_clock_gating()
81 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
86 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
91 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
101 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
108 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
115 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
128 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
137 I915_WRITE(CHICKEN_MISC_2, val); in glk_init_clock_gating()
357 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); in _intel_set_memory_cxsr()
361 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()
370 I915_WRITE(DSPFW3, val); in _intel_set_memory_cxsr()
376 I915_WRITE(FW_BLC_SELF, val); in _intel_set_memory_cxsr()
387 I915_WRITE(INSTPM, val); in _intel_set_memory_cxsr()
875 I915_WRITE(DSPFW1, reg); in pineview_update_wm()
885 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
894 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
903 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
937 I915_WRITE(DSPFW1, in g4x_write_wm_values()
942 I915_WRITE(DSPFW2, in g4x_write_wm_values()
949 I915_WRITE(DSPFW3, in g4x_write_wm_values()
969 I915_WRITE(VLV_DDL(pipe), in vlv_write_wm_values()
981 I915_WRITE(DSPHOWM, 0); in vlv_write_wm_values()
982 I915_WRITE(DSPHOWM1, 0); in vlv_write_wm_values()
983 I915_WRITE(DSPFW4, 0); in vlv_write_wm_values()
984 I915_WRITE(DSPFW5, 0); in vlv_write_wm_values()
985 I915_WRITE(DSPFW6, 0); in vlv_write_wm_values()
987 I915_WRITE(DSPFW1, in vlv_write_wm_values()
992 I915_WRITE(DSPFW2, in vlv_write_wm_values()
996 I915_WRITE(DSPFW3, in vlv_write_wm_values()
1000 I915_WRITE(DSPFW7_CHV, in vlv_write_wm_values()
1003 I915_WRITE(DSPFW8_CHV, in vlv_write_wm_values()
1006 I915_WRITE(DSPFW9_CHV, in vlv_write_wm_values()
1009 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
1021 I915_WRITE(DSPFW7, in vlv_write_wm_values()
1024 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
2247 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | in i965_update_wm()
2251 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | in i965_update_wm()
2254 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); in i965_update_wm()
2382 I915_WRITE(FW_BLC_SELF, in i9xx_update_wm()
2385 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()
2398 I915_WRITE(FW_BLC, fwater_lo); in i9xx_update_wm()
2399 I915_WRITE(FW_BLC2, fwater_hi); in i9xx_update_wm()
2427 I915_WRITE(FW_BLC, fwater_lo); in i845_update_wm()
3462 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); in _ilk_disable_lp_wm()
3467 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); in _ilk_disable_lp_wm()
3472 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); in _ilk_disable_lp_wm()
3502 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); in ilk_write_wm_values()
3504 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); in ilk_write_wm_values()
3506 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); in ilk_write_wm_values()
3509 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); in ilk_write_wm_values()
3511 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); in ilk_write_wm_values()
3513 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); in ilk_write_wm_values()
3522 I915_WRITE(WM_MISC, val); in ilk_write_wm_values()
3529 I915_WRITE(DISP_ARB_CTL2, val); in ilk_write_wm_values()
3539 I915_WRITE(DISP_ARB_CTL, val); in ilk_write_wm_values()
3544 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); in ilk_write_wm_values()
3548 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); in ilk_write_wm_values()
3550 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); in ilk_write_wm_values()
3554 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); in ilk_write_wm_values()
3556 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); in ilk_write_wm_values()
3558 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); in ilk_write_wm_values()
4940 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); in skl_ddb_entry_write()
4942 I915_WRITE(reg, 0); in skl_ddb_entry_write()
4957 I915_WRITE(reg, val); in skl_write_wm_level()
4993 I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0); in skl_write_plane_wm()
5354 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); in skl_atomic_update_crtc_wm()
5999 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6000 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6001 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6099 I915_WRITE(DISP_ARB_CTL2, val); in intel_enable_ipc()
6158 I915_WRITE(RCUPEI, 100000); in ironlake_enable_drps()
6159 I915_WRITE(RCDNEI, 100000); in ironlake_enable_drps()
6162 I915_WRITE(RCBMAXAVG, 90000); in ironlake_enable_drps()
6163 I915_WRITE(RCBMINAVG, 80000); in ironlake_enable_drps()
6165 I915_WRITE(MEMIHYST, 1); in ironlake_enable_drps()
6186 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); in ironlake_enable_drps()
6192 I915_WRITE(VIDSTART, vstart); in ironlake_enable_drps()
6196 I915_WRITE(MEMMODECTL, rgvmodectl); in ironlake_enable_drps()
6222 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); in ironlake_disable_drps()
6223 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); in ironlake_disable_drps()
6224 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); in ironlake_disable_drps()
6225 I915_WRITE(DEIIR, DE_PCU_EVENT); in ironlake_disable_drps()
6226 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); in ironlake_disable_drps()
6232 I915_WRITE(MEMSWCTL, rgvswctl); in ironlake_disable_drps()
6317 I915_WRITE(GEN6_RP_UP_EI, in rps_set_power()
6319 I915_WRITE(GEN6_RP_UP_THRESHOLD, in rps_set_power()
6323 I915_WRITE(GEN6_RP_DOWN_EI, in rps_set_power()
6325 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, in rps_set_power()
6329 I915_WRITE(GEN6_RP_CONTROL, in rps_set_power()
6433 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
6436 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
6439 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
6448 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); in gen6_set_rps()
6449 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in gen6_set_rps()
6465 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in valleyview_set_rps()
6527 I915_WRITE(GEN6_PMINTRMSK, in gen6_rps_busy()
6565 I915_WRITE(GEN6_PMINTRMSK, in gen6_rps_idle()
6628 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_disable_rc6()
6629 I915_WRITE(GEN9_PG_ENABLE, 0); in gen9_disable_rc6()
6634 I915_WRITE(GEN6_RP_CONTROL, 0); in gen9_disable_rps()
6639 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_disable_rc6()
6644 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); in gen6_disable_rps()
6645 I915_WRITE(GEN6_RP_CONTROL, 0); in gen6_disable_rps()
6650 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_disable_rc6()
6655 I915_WRITE(GEN6_RP_CONTROL, 0); in cherryview_disable_rps()
6664 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_disable_rc6()
6671 I915_WRITE(GEN6_RP_CONTROL, 0); in valleyview_disable_rps()
6829 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen9_enable_rps()
6833 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, in gen9_enable_rps()
6836 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); in gen9_enable_rps()
6853 I915_WRITE(GEN6_RC_STATE, 0); in gen9_enable_rc6()
6860 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_enable_rc6()
6864 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); in gen9_enable_rc6()
6865 I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150); in gen9_enable_rc6()
6871 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); in gen9_enable_rc6()
6873 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); in gen9_enable_rc6()
6876 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen9_enable_rc6()
6877 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen9_enable_rc6()
6879 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); in gen9_enable_rc6()
6882 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); in gen9_enable_rc6()
6884 I915_WRITE(GEN6_RC_SLEEP, 0); in gen9_enable_rc6()
6907 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250); in gen9_enable_rc6()
6908 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250); in gen9_enable_rc6()
6911 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ in gen9_enable_rc6()
6919 I915_WRITE(GEN6_RC_CONTROL, in gen9_enable_rc6()
6929 I915_WRITE(GEN9_PG_ENABLE, 0); in gen9_enable_rc6()
6931 I915_WRITE(GEN9_PG_ENABLE, in gen9_enable_rc6()
6943 I915_WRITE(GEN6_RC_STATE, 0); in gen8_enable_rc6()
6950 I915_WRITE(GEN6_RC_CONTROL, 0); in gen8_enable_rc6()
6953 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in gen8_enable_rc6()
6954 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen8_enable_rc6()
6955 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen8_enable_rc6()
6957 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); in gen8_enable_rc6()
6958 I915_WRITE(GEN6_RC_SLEEP, 0); in gen8_enable_rc6()
6959 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ in gen8_enable_rc6()
6963 I915_WRITE(GEN6_RC_CONTROL, in gen8_enable_rc6()
6978 I915_WRITE(GEN6_RPNSWREQ, in gen8_enable_rps()
6980 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen8_enable_rps()
6983 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ in gen8_enable_rps()
6986 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen8_enable_rps()
6990 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ in gen8_enable_rps()
6991 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ in gen8_enable_rps()
6992 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ in gen8_enable_rps()
6993 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ in gen8_enable_rps()
6995 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen8_enable_rps()
6998 I915_WRITE(GEN6_RP_CONTROL, in gen8_enable_rps()
7019 I915_WRITE(GEN6_RC_STATE, 0); in gen6_enable_rc6()
7025 I915_WRITE(GTFIFODBG, gtfifodbg); in gen6_enable_rc6()
7031 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_enable_rc6()
7033 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); in gen6_enable_rc6()
7034 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); in gen6_enable_rc6()
7035 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); in gen6_enable_rc6()
7036 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in gen6_enable_rc6()
7037 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in gen6_enable_rc6()
7040 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); in gen6_enable_rc6()
7042 I915_WRITE(GEN6_RC_SLEEP, 0); in gen6_enable_rc6()
7043 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); in gen6_enable_rc6()
7045 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); in gen6_enable_rc6()
7047 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); in gen6_enable_rc6()
7048 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); in gen6_enable_rc6()
7049 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ in gen6_enable_rc6()
7057 I915_WRITE(GEN6_RC_CONTROL, in gen6_enable_rc6()
7090 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); in gen6_enable_rps()
7091 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen6_enable_rps()
7326 I915_WRITE(VLV_PCBR, pctx_paddr); in cherryview_setup_pctx()
7373 I915_WRITE(VLV_PCBR, pctx_paddr); in valleyview_setup_pctx()
7511 I915_WRITE(GTFIFODBG, gtfifodbg); in cherryview_enable_rc6()
7521 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_enable_rc6()
7524 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in cherryview_enable_rc6()
7525 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in cherryview_enable_rc6()
7526 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in cherryview_enable_rc6()
7529 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); in cherryview_enable_rc6()
7530 I915_WRITE(GEN6_RC_SLEEP, 0); in cherryview_enable_rc6()
7533 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); in cherryview_enable_rc6()
7536 I915_WRITE(VLV_COUNTER_CONTROL, in cherryview_enable_rc6()
7548 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); in cherryview_enable_rc6()
7560 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in cherryview_enable_rps()
7561 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in cherryview_enable_rps()
7562 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in cherryview_enable_rps()
7563 I915_WRITE(GEN6_RP_UP_EI, 66000); in cherryview_enable_rps()
7564 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in cherryview_enable_rps()
7566 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in cherryview_enable_rps()
7569 I915_WRITE(GEN6_RP_CONTROL, in cherryview_enable_rps()
7607 I915_WRITE(GTFIFODBG, gtfifodbg); in valleyview_enable_rc6()
7613 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_enable_rc6()
7615 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); in valleyview_enable_rc6()
7616 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in valleyview_enable_rc6()
7617 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in valleyview_enable_rc6()
7620 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); in valleyview_enable_rc6()
7622 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); in valleyview_enable_rc6()
7625 I915_WRITE(VLV_COUNTER_CONTROL, in valleyview_enable_rc6()
7632 I915_WRITE(GEN6_RC_CONTROL, in valleyview_enable_rc6()
7644 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in valleyview_enable_rps()
7645 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in valleyview_enable_rps()
7646 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in valleyview_enable_rps()
7647 I915_WRITE(GEN6_RP_UP_EI, 66000); in valleyview_enable_rps()
7648 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in valleyview_enable_rps()
7650 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in valleyview_enable_rps()
7652 I915_WRITE(GEN6_RP_CONTROL, in valleyview_enable_rps()
8089 I915_WRITE(ECR, 0); in intel_init_emon()
8093 I915_WRITE(SDEW, 0x15040d00); in intel_init_emon()
8094 I915_WRITE(CSIEW0, 0x007f0000); in intel_init_emon()
8095 I915_WRITE(CSIEW1, 0x1e220004); in intel_init_emon()
8096 I915_WRITE(CSIEW2, 0x04000004); in intel_init_emon()
8099 I915_WRITE(PEW(i), 0); in intel_init_emon()
8101 I915_WRITE(DEW(i), 0); in intel_init_emon()
8126 I915_WRITE(PXW(i), val); in intel_init_emon()
8130 I915_WRITE(OGW0, 0); in intel_init_emon()
8131 I915_WRITE(OGW1, 0); in intel_init_emon()
8132 I915_WRITE(EG0, 0x00007f00); in intel_init_emon()
8133 I915_WRITE(EG1, 0x0000000e); in intel_init_emon()
8134 I915_WRITE(EG2, 0x000e0000); in intel_init_emon()
8135 I915_WRITE(EG3, 0x68000300); in intel_init_emon()
8136 I915_WRITE(EG4, 0x42000000); in intel_init_emon()
8137 I915_WRITE(EG5, 0x00140031); in intel_init_emon()
8138 I915_WRITE(EG6, 0); in intel_init_emon()
8139 I915_WRITE(EG7, 0); in intel_init_emon()
8142 I915_WRITE(PXWL(i), 0); in intel_init_emon()
8145 I915_WRITE(ECR, 0x80000019); in intel_init_emon()
8399 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); in ibx_init_clock_gating()
8407 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
8411 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); in g4x_disable_trickle_feed()
8428 I915_WRITE(PCH_3DCGDIS0, in ilk_init_clock_gating()
8431 I915_WRITE(PCH_3DCGDIS1, in ilk_init_clock_gating()
8441 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
8445 I915_WRITE(DISP_ARB_CTL, in ilk_init_clock_gating()
8458 I915_WRITE(ILK_DISPLAY_CHICKEN1, in ilk_init_clock_gating()
8461 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
8466 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in ilk_init_clock_gating()
8468 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
8471 I915_WRITE(_3D_CHICKEN2, in ilk_init_clock_gating()
8476 I915_WRITE(CACHE_MODE_0, in ilk_init_clock_gating()
8480 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ilk_init_clock_gating()
8497 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | in cpt_init_clock_gating()
8500 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | in cpt_init_clock_gating()
8514 I915_WRITE(TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
8518 I915_WRITE(TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
8537 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in gen6_init_clock_gating()
8539 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
8544 I915_WRITE(_3D_CHICKEN, in gen6_init_clock_gating()
8548 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in gen6_init_clock_gating()
8558 I915_WRITE(GEN6_GT_MODE, in gen6_init_clock_gating()
8561 I915_WRITE(CACHE_MODE_0, in gen6_init_clock_gating()
8564 I915_WRITE(GEN6_UCGCTL1, in gen6_init_clock_gating()
8582 I915_WRITE(GEN6_UCGCTL2, in gen6_init_clock_gating()
8587 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
8595 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
8609 I915_WRITE(ILK_DISPLAY_CHICKEN1, in gen6_init_clock_gating()
8612 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
8615 I915_WRITE(ILK_DSPCLK_GATE_D, in gen6_init_clock_gating()
8642 I915_WRITE(GEN7_FF_THREAD_MODE, reg); in gen7_setup_fixed_func_scheduler()
8652 I915_WRITE(SOUTH_DSPCLK_GATE_D, in lpt_init_clock_gating()
8657 I915_WRITE(TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
8668 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); in lpt_suspend_hw()
8681 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in gen8_set_l3sqc_credits()
8687 I915_WRITE(GEN8_L3SQCREG1, val); in gen8_set_l3sqc_credits()
8695 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in gen8_set_l3sqc_credits()
8701 I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN, in icl_init_clock_gating()
8711 I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | in cnp_init_clock_gating()
8721 I915_WRITE(_3D_CHICKEN3, in cnl_init_clock_gating()
8725 I915_WRITE(GEN8_CHICKEN_DCPR_1, in cnl_init_clock_gating()
8729 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in cnl_init_clock_gating()
8738 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val); in cnl_init_clock_gating()
8743 I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val); in cnl_init_clock_gating()
8749 I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val); in cnl_init_clock_gating()
8758 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in cfl_init_clock_gating()
8768 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in kbl_init_clock_gating()
8773 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | in kbl_init_clock_gating()
8777 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in kbl_init_clock_gating()
8786 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | in skl_init_clock_gating()
8790 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in skl_init_clock_gating()
8802 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in bdw_init_clock_gating()
8805 I915_WRITE(CHICKEN_PAR1_1, in bdw_init_clock_gating()
8810 I915_WRITE(CHICKEN_PIPESL_1(pipe), in bdw_init_clock_gating()
8817 I915_WRITE(GEN7_FF_THREAD_MODE, in bdw_init_clock_gating()
8821 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in bdw_init_clock_gating()
8825 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bdw_init_clock_gating()
8832 I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); in bdw_init_clock_gating()
8835 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) in bdw_init_clock_gating()
8845 I915_WRITE(GEN6_UCGCTL1, in bdw_init_clock_gating()
8852 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); in hsw_init_clock_gating()
8853 I915_WRITE(HSW_ROW_CHICKEN3, in hsw_init_clock_gating()
8857 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in hsw_init_clock_gating()
8862 I915_WRITE(GEN7_FF_THREAD_MODE, in hsw_init_clock_gating()
8866 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in hsw_init_clock_gating()
8869 I915_WRITE(CACHE_MODE_0_GEN7, in hsw_init_clock_gating()
8873 I915_WRITE(CACHE_MODE_1, in hsw_init_clock_gating()
8884 I915_WRITE(GEN7_GT_MODE, in hsw_init_clock_gating()
8888 I915_WRITE(HALF_SLICE_CHICKEN3, in hsw_init_clock_gating()
8892 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in hsw_init_clock_gating()
8901 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); in ivb_init_clock_gating()
8904 I915_WRITE(_3D_CHICKEN3, in ivb_init_clock_gating()
8908 I915_WRITE(IVB_CHICKEN3, in ivb_init_clock_gating()
8914 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in ivb_init_clock_gating()
8918 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ivb_init_clock_gating()
8921 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, in ivb_init_clock_gating()
8925 I915_WRITE(GEN7_L3CNTLREG1, in ivb_init_clock_gating()
8927 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, in ivb_init_clock_gating()
8930 I915_WRITE(GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
8934 I915_WRITE(GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
8936 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, in ivb_init_clock_gating()
8941 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in ivb_init_clock_gating()
8948 I915_WRITE(GEN6_UCGCTL2, in ivb_init_clock_gating()
8952 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in ivb_init_clock_gating()
8962 I915_WRITE(CACHE_MODE_0_GEN7, in ivb_init_clock_gating()
8967 I915_WRITE(CACHE_MODE_1, in ivb_init_clock_gating()
8978 I915_WRITE(GEN7_GT_MODE, in ivb_init_clock_gating()
8984 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); in ivb_init_clock_gating()
8995 I915_WRITE(_3D_CHICKEN3, in vlv_init_clock_gating()
8999 I915_WRITE(IVB_CHICKEN3, in vlv_init_clock_gating()
9005 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in vlv_init_clock_gating()
9010 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in vlv_init_clock_gating()
9013 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in vlv_init_clock_gating()
9017 I915_WRITE(GEN7_ROW_CHICKEN2, in vlv_init_clock_gating()
9021 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in vlv_init_clock_gating()
9031 I915_WRITE(GEN6_UCGCTL2, in vlv_init_clock_gating()
9037 I915_WRITE(GEN7_UCGCTL4, in vlv_init_clock_gating()
9044 I915_WRITE(CACHE_MODE_1, in vlv_init_clock_gating()
9055 I915_WRITE(GEN7_GT_MODE, in vlv_init_clock_gating()
9062 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); in vlv_init_clock_gating()
9069 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); in vlv_init_clock_gating()
9076 I915_WRITE(GEN7_FF_THREAD_MODE, in chv_init_clock_gating()
9081 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in chv_init_clock_gating()
9085 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | in chv_init_clock_gating()
9089 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in chv_init_clock_gating()
9103 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); in chv_init_clock_gating()
9110 I915_WRITE(RENCLK_GATE_D1, 0); in g4x_init_clock_gating()
9111 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | in g4x_init_clock_gating()
9114 I915_WRITE(RAMCLK_GATE_D, 0); in g4x_init_clock_gating()
9120 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); in g4x_init_clock_gating()
9123 I915_WRITE(CACHE_MODE_0, in g4x_init_clock_gating()
9127 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in g4x_init_clock_gating()
9134 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); in i965gm_init_clock_gating()
9135 I915_WRITE(RENCLK_GATE_D2, 0); in i965gm_init_clock_gating()
9136 I915_WRITE(DSPCLK_GATE_D, 0); in i965gm_init_clock_gating()
9137 I915_WRITE(RAMCLK_GATE_D, 0); in i965gm_init_clock_gating()
9139 I915_WRITE(MI_ARB_STATE, in i965gm_init_clock_gating()
9143 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in i965gm_init_clock_gating()
9148 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | in i965g_init_clock_gating()
9153 I915_WRITE(RENCLK_GATE_D2, 0); in i965g_init_clock_gating()
9154 I915_WRITE(MI_ARB_STATE, in i965g_init_clock_gating()
9158 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in i965g_init_clock_gating()
9167 I915_WRITE(D_STATE, dstate); in gen3_init_clock_gating()
9170 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
9173 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); in gen3_init_clock_gating()
9176 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
9179 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); in gen3_init_clock_gating()
9181 I915_WRITE(MI_ARB_STATE, in gen3_init_clock_gating()
9187 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); in i85x_init_clock_gating()
9190 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | in i85x_init_clock_gating()
9193 I915_WRITE(MEM_MODE, in i85x_init_clock_gating()
9199 I915_WRITE(MEM_MODE, in i830_init_clock_gating()