Lines Matching refs:I915_WRITE
100 I915_WRITE(reg, val); in write_data()
163 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); in intel_dsi_host_transfer()
173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); in intel_dsi_host_transfer()
262 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
268 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
374 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
380 I915_WRITE(MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
389 I915_WRITE(MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
426 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
434 I915_WRITE(MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
441 I915_WRITE(MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
452 I915_WRITE(MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
458 I915_WRITE(MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
462 I915_WRITE(MIPI_CTRL(port), val); in glk_dsi_device_ready()
495 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); in bxt_dsi_device_ready()
503 I915_WRITE(MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
506 I915_WRITE(MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
530 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); in vlv_dsi_device_ready()
538 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); in vlv_dsi_device_ready()
541 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); in vlv_dsi_device_ready()
544 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); in vlv_dsi_device_ready()
573 I915_WRITE(MIPI_DEVICE_READY(port), val); in glk_dsi_enter_low_power_mode()
603 I915_WRITE(MIPI_CTRL(PORT_A), tmp); in glk_dsi_disable_mipi_io()
617 I915_WRITE(MIPI_CTRL(port), tmp); in glk_dsi_disable_mipi_io()
640 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in vlv_dsi_clear_device_ready()
644 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in vlv_dsi_clear_device_ready()
648 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in vlv_dsi_clear_device_ready()
664 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); in vlv_dsi_clear_device_ready()
667 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); in vlv_dsi_clear_device_ready()
688 I915_WRITE(MIPI_CTRL(port), temp); in intel_dsi_port_enable()
695 I915_WRITE(VLV_CHICKEN_3, temp); in intel_dsi_port_enable()
720 I915_WRITE(port_ctrl, temp | DPI_ENABLE); in intel_dsi_port_enable()
739 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); in intel_dsi_port_disable()
828 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, in intel_dsi_pre_enable()
832 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_pre_enable()
833 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); in intel_dsi_pre_enable()
842 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_pre_enable()
879 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); in intel_dsi_pre_enable()
981 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_post_disable()
982 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); in intel_dsi_post_disable()
986 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, in intel_dsi_post_disable()
999 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_post_disable()
1360 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), in set_dsi_timings()
1362 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), in set_dsi_timings()
1364 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), in set_dsi_timings()
1368 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); in set_dsi_timings()
1369 I915_WRITE(MIPI_HFP_COUNT(port), hfp); in set_dsi_timings()
1373 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); in set_dsi_timings()
1374 I915_WRITE(MIPI_HBP_COUNT(port), hbp); in set_dsi_timings()
1377 I915_WRITE(MIPI_VFP_COUNT(port), vfp); in set_dsi_timings()
1378 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); in set_dsi_timings()
1379 I915_WRITE(MIPI_VBP_COUNT(port), vbp); in set_dsi_timings()
1432 I915_WRITE(MIPI_CTRL(PORT_A), tmp | in intel_dsi_prepare()
1438 I915_WRITE(MIPI_CTRL(port), tmp | in intel_dsi_prepare()
1447 I915_WRITE(MIPI_CTRL(port), tmp); in intel_dsi_prepare()
1451 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); in intel_dsi_prepare()
1452 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); in intel_dsi_prepare()
1454 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); in intel_dsi_prepare()
1456 I915_WRITE(MIPI_DPI_RESOLUTION(port), in intel_dsi_prepare()
1485 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_prepare()
1506 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1511 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1517 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
1518 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), in intel_dsi_prepare()
1520 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), in intel_dsi_prepare()
1526 I915_WRITE(MIPI_INIT_COUNT(port), in intel_dsi_prepare()
1536 I915_WRITE(MIPI_INIT_COUNT(port == in intel_dsi_prepare()
1542 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); in intel_dsi_prepare()
1545 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); in intel_dsi_prepare()
1552 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), in intel_dsi_prepare()
1561 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1564 I915_WRITE(MIPI_TLPX_TIME_COUNT(port), in intel_dsi_prepare()
1567 I915_WRITE(MIPI_CLK_LANE_TIMING(port), in intel_dsi_prepare()
1576 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); in intel_dsi_prepare()
1578 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), in intel_dsi_prepare()
1586 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), in intel_dsi_prepare()
1606 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); in intel_dsi_unprepare()
1612 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); in intel_dsi_unprepare()
1616 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_unprepare()
1618 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); in intel_dsi_unprepare()