Lines Matching refs:I915_WRITE
279 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
284 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
294 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
299 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
303 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
376 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()
396 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); in _bxt_ddi_phy_init()
401 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); in _bxt_ddi_phy_init()
407 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); in _bxt_ddi_phy_init()
412 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); in _bxt_ddi_phy_init()
430 I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code); in _bxt_ddi_phy_init()
434 I915_WRITE(BXT_PORT_REF_DW8(phy), val); in _bxt_ddi_phy_init()
442 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); in _bxt_ddi_phy_init()
454 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); in bxt_ddi_phy_uninit()
458 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in bxt_ddi_phy_uninit()
609 I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); in bxt_ddi_phy_set_lane_optim_mask()