987 		I915_WRITE(DDI_BUF_TRANS_LO(port, i),  in intel_prepare_dp_ddi_buffers()
989 		I915_WRITE(DDI_BUF_TRANS_HI(port, i),  in intel_prepare_dp_ddi_buffers()
1021 	I915_WRITE(DDI_BUF_TRANS_LO(port, 9),  in intel_prepare_hdmi_ddi_buffers()
1023 	I915_WRITE(DDI_BUF_TRANS_HI(port, 9),  in intel_prepare_hdmi_ddi_buffers()
1127 	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |  in hsw_fdi_link_train()
1135 	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1141 	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1145 	I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);  in hsw_fdi_link_train()
1152 		I915_WRITE(DP_TP_CTL(PORT_E),  in hsw_fdi_link_train()
1162 		I915_WRITE(DDI_BUF_CTL(PORT_E),  in hsw_fdi_link_train()
1171 		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));  in hsw_fdi_link_train()
1175 		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1184 		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);  in hsw_fdi_link_train()
1206 		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1211 		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);  in hsw_fdi_link_train()
1218 		I915_WRITE(DP_TP_CTL(PORT_E), temp);  in hsw_fdi_link_train()
1227 		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);  in hsw_fdi_link_train()
1232 	I915_WRITE(DP_TP_CTL(PORT_E),  in hsw_fdi_link_train()
1710 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);  in intel_ddi_set_pipe_settings()
1726 	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);  in intel_ddi_set_vc_payload_alloc()
1812 	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);  in intel_ddi_enable_transcoder_func()
1825 	I915_WRITE(reg, val);  in intel_ddi_disable_transcoder_func()
1858 	I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);  in intel_ddi_toggle_hdcp_signalling()
2055 		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),  in intel_ddi_enable_pipe_clock()
2065 		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),  in intel_ddi_disable_pipe_clock()
2080 	I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);  in _skl_ddi_set_iboost()
2237 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);  in cnl_ddi_vswing_program()
2247 	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);  in cnl_ddi_vswing_program()
2258 		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);  in cnl_ddi_vswing_program()
2267 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);  in cnl_ddi_vswing_program()
2273 	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);  in cnl_ddi_vswing_program()
2304 	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);  in cnl_ddi_vswing_sequence()
2321 		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);  in cnl_ddi_vswing_sequence()
2327 	I915_WRITE(CNL_PORT_CL1CM_DW5, val);  in cnl_ddi_vswing_sequence()
2332 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);  in cnl_ddi_vswing_sequence()
2340 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);  in cnl_ddi_vswing_sequence()
2364 	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);  in icl_ddi_combo_vswing_program()
2378 	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);  in icl_ddi_combo_vswing_program()
2388 	I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);  in icl_ddi_combo_vswing_program()
2397 		I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);  in icl_ddi_combo_vswing_program()
2432 	I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);  in icl_combo_phy_ddi_vswing_sequence()
2449 		I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);  in icl_combo_phy_ddi_vswing_sequence()
2455 	I915_WRITE(ICL_PORT_CL_DW5(port), val);  in icl_combo_phy_ddi_vswing_sequence()
2460 	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);  in icl_combo_phy_ddi_vswing_sequence()
2468 	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);  in icl_combo_phy_ddi_vswing_sequence()
2565 			I915_WRITE(DPCLKA_CFGCR0_ICL, val);  in icl_map_plls_to_ports()
2570 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);  in icl_map_plls_to_ports()
2595 		I915_WRITE(DPCLKA_CFGCR0_ICL,  in icl_unmap_plls_to_ports()
2616 			I915_WRITE(DDI_CLK_SEL(port),  in intel_ddi_clk_select()
2623 		I915_WRITE(DPCLKA_CFGCR0, val);  in intel_ddi_clk_select()
2632 		I915_WRITE(DPCLKA_CFGCR0, val);  in intel_ddi_clk_select()
2642 		I915_WRITE(DPLL_CTRL2, val);  in intel_ddi_clk_select()
2645 		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));  in intel_ddi_clk_select()
2658 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);  in intel_ddi_clk_disable()
2660 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |  in intel_ddi_clk_disable()
2663 		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |  in intel_ddi_clk_disable()
2666 		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);  in intel_ddi_clk_disable()
2791 		I915_WRITE(DDI_BUF_CTL(port), val);  in intel_disable_ddi_buf()
2798 	I915_WRITE(DP_TP_CTL(port), val);  in intel_disable_ddi_buf()
2898 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);  in intel_ddi_fdi_post_disable()
2906 	I915_WRITE(FDI_RX_MISC(PIPE_A), val);  in intel_ddi_fdi_post_disable()
2910 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);  in intel_ddi_fdi_post_disable()
2914 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);  in intel_ddi_fdi_post_disable()
2978 		I915_WRITE(CHICKEN_TRANS(transcoder), val);  in intel_enable_ddi_hdmi()
2990 		I915_WRITE(CHICKEN_TRANS(transcoder), val);  in intel_enable_ddi_hdmi()
2997 	I915_WRITE(DDI_BUF_CTL(port),  in intel_enable_ddi_hdmi()
3086 			I915_WRITE(DDI_BUF_CTL(port), val);  in intel_ddi_prepare_link_retrain()
3093 		I915_WRITE(DP_TP_CTL(port), val);  in intel_ddi_prepare_link_retrain()
3109 	I915_WRITE(DP_TP_CTL(port), val);  in intel_ddi_prepare_link_retrain()
3113 	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);  in intel_ddi_prepare_link_retrain()