169 	I915_WRITE(VIDEO_DIP_CTL, val);  in g4x_write_infoframe()
173 		I915_WRITE(VIDEO_DIP_DATA, *data);  in g4x_write_infoframe()
178 		I915_WRITE(VIDEO_DIP_DATA, 0);  in g4x_write_infoframe()
185 	I915_WRITE(VIDEO_DIP_CTL, val);  in g4x_write_infoframe()
226 	I915_WRITE(reg, val);  in ibx_write_infoframe()
230 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in ibx_write_infoframe()
235 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);  in ibx_write_infoframe()
242 	I915_WRITE(reg, val);  in ibx_write_infoframe()
289 	I915_WRITE(reg, val);  in cpt_write_infoframe()
293 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in cpt_write_infoframe()
298 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);  in cpt_write_infoframe()
305 	I915_WRITE(reg, val);  in cpt_write_infoframe()
344 	I915_WRITE(reg, val);  in vlv_write_infoframe()
348 		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in vlv_write_infoframe()
353 		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);  in vlv_write_infoframe()
360 	I915_WRITE(reg, val);  in vlv_write_infoframe()
399 	I915_WRITE(ctl_reg, val);  in hsw_write_infoframe()
403 		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,  in hsw_write_infoframe()
409 		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,  in hsw_write_infoframe()
414 	I915_WRITE(ctl_reg, val);  in hsw_write_infoframe()
577 		I915_WRITE(reg, val);  in g4x_set_infoframes()
596 	I915_WRITE(reg, val);  in g4x_set_infoframes()
687 	I915_WRITE(reg, val);  in intel_hdmi_set_gcp_infoframe()
716 		I915_WRITE(reg, val);  in ibx_set_infoframes()
737 	I915_WRITE(reg, val);  in ibx_set_infoframes()
767 		I915_WRITE(reg, val);  in cpt_set_infoframes()
780 	I915_WRITE(reg, val);  in cpt_set_infoframes()
812 		I915_WRITE(reg, val);  in vlv_set_infoframes()
833 	I915_WRITE(reg, val);  in vlv_set_infoframes()
858 		I915_WRITE(reg, val);  in hsw_set_infoframes()
866 	I915_WRITE(reg, val);  in hsw_set_infoframes()
1111 	I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);  in intel_hdmi_hdcp_check_link()
1171 	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);  in intel_hdmi_prepare()
1272 	I915_WRITE(intel_hdmi->hdmi_reg, temp);  in g4x_enable_hdmi()
1298 	I915_WRITE(intel_hdmi->hdmi_reg, temp);  in ibx_enable_hdmi()
1300 	I915_WRITE(intel_hdmi->hdmi_reg, temp);  in ibx_enable_hdmi()
1312 		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);  in ibx_enable_hdmi()
1319 		I915_WRITE(intel_hdmi->hdmi_reg, temp);  in ibx_enable_hdmi()
1321 		I915_WRITE(intel_hdmi->hdmi_reg, temp);  in ibx_enable_hdmi()
1357 		I915_WRITE(TRANS_CHICKEN1(pipe),  in cpt_enable_hdmi()
1365 	I915_WRITE(intel_hdmi->hdmi_reg, temp);  in cpt_enable_hdmi()
1372 		I915_WRITE(intel_hdmi->hdmi_reg, temp);  in cpt_enable_hdmi()
1375 		I915_WRITE(TRANS_CHICKEN1(pipe),  in cpt_enable_hdmi()
1405 	I915_WRITE(intel_hdmi->hdmi_reg, temp);  in intel_disable_hdmi()
1427 		I915_WRITE(intel_hdmi->hdmi_reg, temp);  in intel_disable_hdmi()
1429 		I915_WRITE(intel_hdmi->hdmi_reg, temp);  in intel_disable_hdmi()
1433 		I915_WRITE(intel_hdmi->hdmi_reg, temp);  in intel_disable_hdmi()
2395 		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);  in intel_hdmi_init_connector()