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/Linux-v5.10/drivers/isdn/mISDN/
Dlayer2.c92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
124 l2_newid(struct layer2 *l2) in l2_newid() argument
128 id = l2->next_id++; in l2_newid()
[all …]
Dtei.c109 struct layer2 *l2; in da_deactivate() local
113 list_for_each_entry(l2, &mgr->layer2, list) { in da_deactivate()
114 if (l2->l2m.state > ST_L2_4) { in da_deactivate()
146 struct layer2 *l2; in da_timer() local
151 list_for_each_entry(l2, &mgr->layer2, list) { in da_timer()
152 if (l2->l2m.state > ST_L2_4) { in da_timer()
234 tm->l2->sapi, tm->l2->tei, &vaf); in tei_debug()
246 struct layer2 *l2; in get_free_id() local
248 list_for_each_entry(l2, &mgr->layer2, list) { in get_free_id()
249 if (l2->ch.nr > 63) { in get_free_id()
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/Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
16 "fsl,b4860-l2-cache-controller"
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen1/
Dcache.json15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
58 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
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Drecommended.json17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
65 "BriefDescription": "All L2 Cache Hits",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
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/Linux-v5.10/drivers/memory/
Dbt1-l2-ctl.c8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
77 static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val) in l2_ctl_get_latency() argument
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
103 static int l2_ctl_set_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 val) in l2_ctl_set_latency() argument
130 ret = regmap_update_bits(l2->sys_regs, L2_CTL_REG, mask, data); in l2_ctl_set_latency()
134 return regmap_read_poll_timeout(l2->sys_regs, L2_CTL_REG, data, in l2_ctl_set_latency()
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen2/
Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
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Drecommended.json17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
65 "BriefDescription": "All L2 Cache Hits",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/bonnell/
Dcache.json8 "BriefDescription": "Cycles L2 address bus is in use."
16 "BriefDescription": "Cycles the L2 cache data bus is busy."
24 "BriefDescription": "Cycles the L2 transfers data to the core."
32 "BriefDescription": "L2 cache misses."
40 "BriefDescription": "L2 cache misses."
48 "BriefDescription": "L2 cache misses."
56 "BriefDescription": "L2 cache line modifications."
64 "BriefDescription": "L2 cache lines evicted."
72 "BriefDescription": "L2 cache lines evicted."
80 "BriefDescription": "L2 cache lines evicted."
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmont/
Dcache.json4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
170 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
176 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
194 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
200 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
230 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
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/Linux-v5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dcache.json9 …LB refill. This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes r…
27 … data TLB refill. This event counts any refill of the data L1 TLB from the L2 TLB. This includes r…
39 …e-Back. This event counts any write-back of data from the L1 data cache to L2 or L3. This counts b…
45 …tion": "L2 data cache access. This event counts any transaction from L1 which looks up in the L2 c…
48 "BriefDescription": "L2 data cache access"
51 …L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be …
54 "BriefDescription": "L2 data cache refill"
57 …L2 data cache write-back. This event counts any write-back of data from the L2 cache to outside th…
60 "BriefDescription": "L2 data cache write-back"
63 …L2 data cache allocation without refill. This event counts any full cache line write into the L2 c…
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmontplus/
Dcache.json4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
12 "BriefDescription": "L2 cache request misses"
16 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
24 "BriefDescription": "L2 cache requests"
28 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
192 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
199 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
218 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
225 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
257 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
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/Linux-v5.10/arch/powerpc/sysdev/
Dfsl_85xx_l2ctlr.c5 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
75 dev_err(&dev->dev, "Missing L2 cache-size\n"); in mpc85xx_l2ctlr_of_probe()
81 return 0; /* fall back to L2 cache only */ in mpc85xx_l2ctlr_of_probe()
92 dev_err(&dev->dev, "Can't map L2 controller\n"); in mpc85xx_l2ctlr_of_probe()
152 dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n"); in mpc85xx_l2ctlr_of_remove()
159 .compatible = "fsl,p2020-l2-cache-controller",
162 .compatible = "fsl,p2010-l2-cache-controller",
165 .compatible = "fsl,p1020-l2-cache-controller",
168 .compatible = "fsl,p1011-l2-cache-controller",
171 .compatible = "fsl,p1013-l2-cache-controller",
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/knightslanding/
Dcache.json8 … a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictio…
16 … number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condit…
24 "BriefDescription": "Counts the total number of L2 cache references."
32 "BriefDescription": "Counts the number of L2 cache misses"
59 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
69 "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
135 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
146 …rwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid …
157 … responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
168 …esponses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/silvermont/
Dcache.json3 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
9 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ"
12 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
21 …his event counts requests originating from the core that references a cache line in the L2 cache.",
27 "BriefDescription": "L2 cache requests from this core"
30 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
36 "BriefDescription": "L2 cache request misses"
132 "PublicDescription": "This event counts the number of load ops retired that hit in the L2.",
138 "BriefDescription": "Loads hit L2"
142 … "PublicDescription": "This event counts the number of load ops retired that miss in the L2.",
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellde/
Dcache.json5 "BriefDescription": "Demand Data Read miss L2, no rejects",
8 …ion": "This event counts the number of demand Data Read requests that miss L2 cache. Only not reje…
15 "BriefDescription": "RFO requests that miss L2 cache.",
24 "BriefDescription": "L2 cache misses when fetching instructions.",
33 "BriefDescription": "Demand requests that miss L2 cache.",
42 "BriefDescription": "L2 prefetch requests that miss L2 cache",
45 …tion": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cac…
52 "BriefDescription": "All requests that miss L2 cache.",
61 "BriefDescription": "Demand Data Read requests that hit L2 cache",
64 …"PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache.…
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/Linux-v5.10/Documentation/devicetree/bindings/memory-controllers/
Dbaikal,bt1-l2-ctl.yaml5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
8 title: Baikal-T1 L2-cache Control Block
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
17 L2-cache controller block is responsible for the tuning. Its DT node is
22 const: baikal,bt1-l2-ctl
27 baikal,l2-ws-latency:
34 baikal,l2-tag-latency:
41 baikal,l2-data-latency:
55 l2@1f04d028 {
56 compatible = "baikal,bt1-l2-ctl";
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/Linux-v5.10/tools/perf/pmu-events/arch/powerpc/power8/
Dcache.json5 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
6 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
11 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
12 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load…
36 …ssor's data cache was reloaded from a location other than the local core's L2 due to either only d…
41 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/ivybridge/
Dcache.json3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
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/Linux-v5.10/arch/mips/cavium-octeon/
DKconfig30 bool "Lock often used kernel code in the L2"
33 Enable locking parts of the kernel into the L2 cache.
36 bool "Lock the TLB handler in L2"
40 Lock the low level TLB fast path into L2.
43 bool "Lock the exception handler in L2"
47 Lock the low level exception handler into L2.
50 bool "Lock the interrupt handler in L2"
54 Lock the low level interrupt handler into L2.
57 bool "Lock the 2nd level interrupt handler in L2"
61 Lock the 2nd level interrupt handler in L2.
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/haswellx/
Dcache.json5 "BriefDescription": "Demand Data Read miss L2, no rejects",
9 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
16 "BriefDescription": "RFO requests that miss L2 cache",
19 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
26 "BriefDescription": "L2 cache misses when fetching instructions",
29 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
36 "BriefDescription": "Demand requests that miss L2 cache",
40 "PublicDescription": "Demand requests that miss L2 cache.",
47 "BriefDescription": "L2 prefetch requests that miss L2 cache",
50 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/haswell/
Dcache.json3 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
10 "BriefDescription": "Demand Data Read miss L2, no rejects",
14 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
20 "BriefDescription": "RFO requests that miss L2 cache",
24 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
30 "BriefDescription": "L2 cache misses when fetching instructions",
34 "PublicDescription": "Demand requests that miss L2 cache.",
41 "BriefDescription": "Demand requests that miss L2 cache",
45 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
51 "BriefDescription": "L2 prefetch requests that miss L2 cache",
[all …]
/Linux-v5.10/arch/parisc/lib/
Dio.c169 unsigned int l = 0, l2; in insw() local
221 l2 = cpu_to_le16(inw(port)); in insw()
222 *(unsigned short *)p = (l & 0xff) << 8 | (l2 >> 8); in insw()
224 l = l2; in insw()
241 unsigned int l = 0, l2; in insl() local
268 l2 = cpu_to_le32(inl(port)); in insl()
269 *(unsigned int *)p = (l & 0xffff) << 16 | (l2 >> 16); in insl()
271 l = l2; in insl()
285 l2 = cpu_to_le32(inl(port)); in insl()
286 *(unsigned int *)p = (l & 0xff) << 24 | (l2 >> 8); in insl()
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/ivytown/
Dcache.json3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellx/
Dcache.json5 "BriefDescription": "Demand Data Read miss L2, no rejects",
8 …ion": "This event counts the number of demand Data Read requests that miss L2 cache. Only not reje…
15 "BriefDescription": "RFO requests that miss L2 cache.",
24 "BriefDescription": "L2 cache misses when fetching instructions.",
33 "BriefDescription": "Demand requests that miss L2 cache.",
42 "BriefDescription": "L2 prefetch requests that miss L2 cache",
45 …tion": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cac…
52 "BriefDescription": "All requests that miss L2 cache.",
61 "BriefDescription": "Demand Data Read requests that hit L2 cache",
64 …ounts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
[all …]

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