Lines Matching full:l2
5 "BriefDescription": "Demand Data Read miss L2, no rejects",
9 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
16 "BriefDescription": "RFO requests that miss L2 cache",
19 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
26 "BriefDescription": "L2 cache misses when fetching instructions",
29 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
36 "BriefDescription": "Demand requests that miss L2 cache",
40 "PublicDescription": "Demand requests that miss L2 cache.",
47 "BriefDescription": "L2 prefetch requests that miss L2 cache",
50 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
57 "BriefDescription": "All requests that miss L2 cache",
61 "PublicDescription": "All requests that missed L2.",
68 "BriefDescription": "Demand Data Read requests that hit L2 cache",
72 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
79 "BriefDescription": "RFO requests that hit L2 cache",
82 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
89 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
92 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
99 "BriefDescription": "L2 prefetch requests that hit L2 cache",
102 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
113 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
120 "BriefDescription": "RFO requests to L2 cache",
123 "PublicDescription": "Counts all L2 store RFO requests.",
130 "BriefDescription": "L2 code requests",
133 "PublicDescription": "Counts all L2 code requests.",
140 "BriefDescription": "Demand requests to L2 cache",
144 "PublicDescription": "Demand requests to L2 cache.",
151 "BriefDescription": "Requests from L2 hardware prefetchers",
154 "PublicDescription": "Counts all L2 HW prefetcher requests.",
161 "BriefDescription": "All L2 requests",
165 "PublicDescription": "All requests to L2 cache.",
172 "BriefDescription": "Not rejected writebacks that hit L2 cache",
175 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
518 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
556 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
562 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
691 "BriefDescription": "Demand Data Read requests that access L2 cache",
694 "PublicDescription": "Demand data read requests that access L2 cache.",
701 "BriefDescription": "RFO requests that access L2 cache",
704 "PublicDescription": "RFO requests that access L2 cache.",
711 "BriefDescription": "L2 cache accesses when fetching instructions",
714 "PublicDescription": "L2 cache accesses when fetching instructions.",
721 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
724 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
731 "BriefDescription": "L1D writebacks that access L2 cache",
734 "PublicDescription": "L1D writebacks that access L2 cache.",
741 "BriefDescription": "L2 fill requests that access L2 cache",
744 "PublicDescription": "L2 fill requests that access L2 cache.",
751 "BriefDescription": "L2 writebacks that access L2 cache",
754 "PublicDescription": "L2 writebacks that access L2 cache.",
761 "BriefDescription": "Transactions accessing L2 pipe",
764 "PublicDescription": "Transactions accessing L2 pipe.",
771 "BriefDescription": "L2 cache lines in I state filling L2",
774 "PublicDescription": "L2 cache lines in I state filling L2.",
781 "BriefDescription": "L2 cache lines in S state filling L2",
784 "PublicDescription": "L2 cache lines in S state filling L2.",
791 "BriefDescription": "L2 cache lines in E state filling L2",
794 "PublicDescription": "L2 cache lines in E state filling L2.",
801 "BriefDescription": "L2 cache lines filling L2",
804 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
811 "BriefDescription": "Clean L2 cache lines evicted by demand",
814 "PublicDescription": "Clean L2 cache lines evicted by demand.",
821 "BriefDescription": "Dirty L2 cache lines evicted by demand",
824 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
919 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
924 "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
932 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
937 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",