Lines Matching full:l2
5 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
6 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different…
11 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
12 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load…
36 …ssor's data cache was reloaded from a location other than the local core's L2 due to either only d…
41 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
42 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit s…
47 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch co…
48 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch c…
53 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without disp…
54 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dis…
59 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict…
60 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflic…
71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
107 …data cache was reloaded either shared or modified data from another core's L2/L3 on a different ch…
108 …data cache was reloaded either shared or modified data from another core's L2/L3 on a different ch…
113 …data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip …
114 …data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip …
119 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same No…
120 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same No…
125 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same No…
126 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same No…