Lines Matching full:l2
4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
170 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
176 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
194 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
200 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
230 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
241 …d, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_…
249 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
254 …d, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
262 …d, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
267 …d, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
275 …d, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
280 …ad for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop m…
288 …ad for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop m…
293 …ad, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_…
301 …read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
306 …ounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_…
314 …cription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
319 …ounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
327 …ounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
332 …ounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
340 …ounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop h…
345 …ds for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop m…
353 …ds for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop m…
358 …Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_…
366 …scription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
371 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_O…
379 "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.",
384 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hi…
392 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit…
397 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hi…
405 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit…
410 …"PublicDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a…
418 …"BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a …
423 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF…
431 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.",
436 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. …
444 … "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.",
449 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache w…
457 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
462 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache w…
470 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
475 …blicDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 c…
483 …riefDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 c…
488 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. R…
496 … "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.",
501 …"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop …
509 …"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop h…
514 …"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop …
522 …"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop h…
527 …"PublicDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with…
535 …"BriefDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with …
540 …"PublicDescription": "Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_…
548 "BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.",
566 … writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_…
574 …unts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.",
579 …a writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_…
587 …ounts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.",
592 … writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_…
600 …che line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.",
605 … writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop h…
613 … writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop h…
618 … writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop h…
626 … writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop h…
631 …o uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop m…
639 …o uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop m…
644 …a writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_…
652 …ache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.",
657 …he line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_…
665 …unts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.",
670 …he line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop h…
678 …he line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop h…
683 …he line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop h…
691 …he line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop h…
696 …eads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop m…
704 …eads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop m…
709 …che line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_…
717 …ounts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.",
722 … data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_…
730 …ion": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache.",
735 … data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop h…
743 … data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop h…
748 … data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop h…
756 … data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop h…
761 …he lines requests by software prefetch instructions that true miss for the L2 cache with a snoop m…
769 …he lines requests by software prefetch instructions that true miss for the L2 cache with a snoop m…
774 …s data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_…
782 …tion": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache.",
787 …(USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_…
795 …te combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.",
800 …(USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop h…
808 …(USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop h…
813 …(USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop h…
821 …(USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop h…
826 …mory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop m…
834 …mory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop m…
839 … (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_…
847 …ite combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.",
865 …write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_…
873 …ble (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.",
878 …able (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_…
886 …ta in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.",
891 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.…
899 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.…
904 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache …
912 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache …
917 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache …
925 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache …
930 … "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 c…
938 … "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 c…
943 …ion": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.…
951 …ion": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.…
956 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cac…
964 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cac…
969 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cac…
977 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cac…
982 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cac…
990 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cac…
995 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L…
1003 …": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L…
1008 …ption": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cac…
1016 …ption": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cac…
1021 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cac…
1029 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cac…
1034 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cac…
1042 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cac…
1047 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cac…
1055 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cac…
1060 … the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2…
1068 … the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2…
1073 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cach…
1081 …ounts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cach…
1086 …he instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any res…
1094 …he instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any res…
1099 …and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_…
1107 …on cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache.",
1112 …and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop h…
1120 …and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop h…
1125 …e prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop m…
1133 …e prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop m…
1138 … and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_…
1146 …ion cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache.",
1151 …full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any res…
1159 …full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any res…
1164 … (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_…
1172 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.",
1177 … (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop h…
1185 … (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop h…
1190 … (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop h…
1198 … (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop h…
1203 …quests generated by a write to full data cache line that true miss for the L2 cache with a snoop m…
1211 …quests generated by a write to full data cache line that true miss for the L2 cache with a snoop m…
1216 …p (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_…
1224 … for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.",
1229 … of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any res…
1237 … of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any res…
1242 …on": "Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_…
1250 …riefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache.",
1255 …on": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop h…
1263 …on": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop h…
1268 …on": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop h…
1276 …on": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop h…
1281 …nts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop m…
1289 …nts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop m…
1294 …ion": "Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_…
1302 …"BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.…