Lines Matching full:l2
4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
12 "BriefDescription": "L2 cache request misses"
16 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
24 "BriefDescription": "L2 cache requests"
28 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
192 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
199 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
218 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
225 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
257 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
284 …"PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Req…
294 … "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.",
299 … "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop m…
309 … "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop m…
314 …"PublicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache wit…
324 …"BriefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with…
329 …ata reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any res…
339 …ata reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any res…
359 …ership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_…
369 …reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.",
374 …O) requests generated by a write to full data cache line true miss for the L2 cache with a snoop m…
384 …O) requests generated by a write to full data cache line true miss for the L2 cache with a snoop m…
389 …rship (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop h…
399 …rship (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop h…
404 …write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any res…
414 …write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any res…
434 …eline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_…
444 …truction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache.",
449 …I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop m…
459 …I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop m…
464 …line and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop h…
474 …line and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop h…
479 …at miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any res…
489 …at miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any res…
494 …"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictio…
504 …"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache eviction…
509 … "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.…
519 … "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.…
524 …nts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 c…
534 …nts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 c…
539 …"Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache …
549 …"Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache …
554 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
564 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
569 …"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have a…
579 …"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have an…
584 …ription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.…
594 …ription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.…
599 …on": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 c…
609 …on": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 c…
614 …ription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache…
624 …ription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache…
629 …data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the ti…
639 …data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the ti…
644 …"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have an…
654 …"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any…
659 …ption": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Re…
669 …ription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.",
674 …": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cach…
684 …": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cach…
689 …ption": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache wi…
699 …ption": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache wi…
704 …ads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time …
714 …ads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time …
734 …"PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCO…
744 "BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.",
749 …"PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a sn…
759 …"BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a sno…
764 …"PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit i…
774 …"BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in…
779 … lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any res…
789 … lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any res…
809 …ining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_…
819 …le write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache.",
824 …C) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop m…
834 …C) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop m…
839 …ning (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop h…
849 …ning (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop h…
854 …ache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any res…
864 …ache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any res…
884 …Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_…
894 …scription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache.",
899 …a cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop m…
909 …a cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop m…
914 …ounts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop h…
924 …ounts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop h…
929 …oftware prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any res…
939 …oftware prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any res…
959 …ta cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_…
969 …": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache.",
974 …ine reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop m…
984 …ine reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop m…
989 …a cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop h…
999 …a cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop h…
1004 …ware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any res…
1014 …ware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any res…
1034 …y data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_…
1044 …": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache.",
1049 …tes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop m…
1059 …tes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop m…
1064 … data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop h…
1074 … data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop h…
1079 …mbining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any res…
1089 …mbining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any res…
1109 …"PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCO…
1119 "BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.",
1124 …"PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a sn…
1134 …"BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a sno…
1139 …"PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit i…
1149 …"BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in…
1154 …uests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any res…
1164 …uests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any res…
1169 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction res…
1179 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction resp…
1184 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requir…
1194 "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.",
1199 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cac…
1209 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cach…
1214 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a…
1224 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a …
1229 …tion": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time …
1239 …tion": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time …
1259 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE…
1269 "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.",
1274 …"PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoo…
1284 …"BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop…
1289 …"PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in …
1299 …"BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in t…
1304 …ata reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
1314 …ata reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
1334 …n": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_…
1344 …iefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
1349 …s reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop m…
1359 …s reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop m…
1364 …": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h…
1374 …": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h…
1379 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
1389 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
1409 …de read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_…
1419 …data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
1424 …nd read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop m…
1434 …nd read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop m…
1439 …e read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h…
1449 …e read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h…
1454 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
1464 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…