Lines Matching full:l2
3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
59 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
63 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
69 "BriefDescription": "L2 cache misses when fetching instructions",
73 "PublicDescription": "Counts all L2 code requests.",
79 "BriefDescription": "L2 code requests",
83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
89 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
93 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
99 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
103 "PublicDescription": "Counts all L2 HW prefetcher requests.",
109 "BriefDescription": "Requests from L2 hardware prefetchers",
149 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
153 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
159 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
163 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
169 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
178 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
496 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
526 "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
626 "PublicDescription": "Demand Data Read requests that access L2 cache.",
632 "BriefDescription": "Demand Data Read requests that access L2 cache",
636 "PublicDescription": "RFO requests that access L2 cache.",
642 "BriefDescription": "RFO requests that access L2 cache",
646 "PublicDescription": "L2 cache accesses when fetching instructions.",
652 "BriefDescription": "L2 cache accesses when fetching instructions",
656 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
662 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
666 "PublicDescription": "L1D writebacks that access L2 cache.",
672 "BriefDescription": "L1D writebacks that access L2 cache",
676 "PublicDescription": "L2 fill requests that access L2 cache.",
682 "BriefDescription": "L2 fill requests that access L2 cache",
686 "PublicDescription": "L2 writebacks that access L2 cache.",
692 "BriefDescription": "L2 writebacks that access L2 cache",
696 "PublicDescription": "Transactions accessing L2 pipe.",
702 "BriefDescription": "Transactions accessing L2 pipe",
706 "PublicDescription": "L2 cache lines in I state filling L2.",
712 "BriefDescription": "L2 cache lines in I state filling L2",
716 "PublicDescription": "L2 cache lines in S state filling L2.",
722 "BriefDescription": "L2 cache lines in S state filling L2",
726 "PublicDescription": "L2 cache lines in E state filling L2.",
732 "BriefDescription": "L2 cache lines in E state filling L2",
736 "PublicDescription": "L2 cache lines filling L2.",
742 "BriefDescription": "L2 cache lines filling L2",
746 "PublicDescription": "Clean L2 cache lines evicted by demand.",
752 "BriefDescription": "Clean L2 cache lines evicted by demand",
756 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
762 "BriefDescription": "Dirty L2 cache lines evicted by demand",
766 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
772 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
776 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
782 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
786 "PublicDescription": "Dirty L2 cache lines filling the L2.",
792 "BriefDescription": "Dirty L2 cache lines filling the L2",
1077 …"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core…
1101 … "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
1113 … "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
1125 …"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and th…
1137 …"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and th…
1149 …"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and si…
1161 …"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and th…