Lines Matching full:l2
5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
82 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-…
88 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
94 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
100 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
106 …"BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divide…
112 …"BriefDescription": "LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining …
118 …"BriefDescription": "LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining …
124 …"BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write …
130 …"BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Wri…
136 …BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data c…
142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
148 …fDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache…
154 …Description": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache …
160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
166 …Description": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction…
172 …efDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instructi…
178 …iefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruct…
184 …BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instru…
190 …"Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request…
196 … "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache reques…
202 …ription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in …
208 "BriefDescription": "L2 prefetch hit in L2.",
214 …"BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipelin…
220 …"BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline whi…
236 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
246 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
251 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs.",
257 …"BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instr…
263 …"BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instr…
269 …"BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instr…
298 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…