| /Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
[all …]
|
| D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
15 I/O space utilized by the controller. The size should
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
31 - reg : <prop-encoded-array>
[all …]
|
| /Linux-v5.10/arch/powerpc/sysdev/ |
| D | fsl_85xx_l2ctlr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
5 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
27 return -EINVAL; in get_cache_sram_params()
30 return -EINVAL; in get_cache_sram_params()
32 sram_params->sram_offset = addr; in get_cache_sram_params()
33 sram_params->sram_size = size; in get_cache_sram_params()
56 __setup("cache-sram-size=", get_size_from_cmdline);
57 __setup("cache-sram-offset=", get_offset_from_cmdline);
68 if (!dev->dev.of_node) { in mpc85xx_l2ctlr_of_probe()
[all …]
|
| /Linux-v5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
|
| /Linux-v5.10/Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 1 * Andestech L2 cache Controller
3 The level-2 cache controller plays an important role in reducing memory latency
5 Level-2 cache controller in general enhances overall system performance
10 representation of an Andestech L2 cache controller.
13 - compatible:
17 - reg : Physical base address and size of cache controller's memory mapped
18 - cache-unified : Specifies the cache is a unified cache.
19 - cache-level : Should be set to 2 for a level 2 cache.
23 cache-controller@e0500000 {
26 cache-unified;
[all …]
|
| /Linux-v5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
|
| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
[all …]
|
| /Linux-v5.10/Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
17 of memory for masters in a Core Complex. The Level 2 Cache Controller also
[all …]
|
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
[all …]
|
| /Linux-v5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hip05.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| /Linux-v5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
[all …]
|
| D | fsl-ls2088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a72";
30 cpu-idle-states = <&CPU_PW20>;
31 next-level-cache = <&cluster0_l2>;
[all …]
|
| /Linux-v5.10/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
[all …]
|
| /Linux-v5.10/drivers/edac/ |
| D | mpc85xx_edac.c | 2 * Freescale MPC85xx Memory Controller kernel module
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
51 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; in mpc85xx_pci_check()
54 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); in mpc85xx_pci_check()
58 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check()
66 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); in mpc85xx_pci_check()
68 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check()
70 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); in mpc85xx_pci_check()
72 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check()
74 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check()
[all …]
|
| D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
[all …]
|
| /Linux-v5.10/arch/arm64/boot/dts/qcom/ |
| D | sdm660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <19200000>;
23 clock-output-names = "xo_board";
[all …]
|
| /Linux-v5.10/arch/arm/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
[all …]
|
| /Linux-v5.10/arch/riscv/boot/dts/kendryte/ |
| D | k210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/k210-clk.h>
10 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13 #address-cells = <1>;
14 #size-cells = <1>;
23 * Since this is a non-ratified draft specification, the kernel does not
28 #address-cells = <1>;
29 #size-cells = <0>;
30 timebase-frequency = <7800000>;
36 mmu-type = "none";
[all …]
|
| /Linux-v5.10/drivers/soc/qcom/ |
| D | rpmh-internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
24 * to the controller
26 * @drv: The controller.
27 * @type: Type of the TCS in this group - active, sleep, wake.
35 * Start: grab drv->lock, set req, set tcs_in_use, drop drv->lock,
38 * grab drv->lock, clear tcs_in_use, drop drv->lock
56 * struct rpmh_request: the message to be sent to rpmh-rsc
62 * @err: err return from the controller
75 * struct rpmh_ctrlr: our representation of the controller
[all …]
|
| /Linux-v5.10/arch/arm/boot/dts/ |
| D | arm-realview-eb-mp.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
40 /* Primary interrupt controller in the test chip */
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
[all …]
|
| D | bcm63138.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
|
| D | highbank.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
[all …]
|
| /Linux-v5.10/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,llcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
17 common pool of memory. Cache memory is divided into partitions called slices
24 - qcom,sc7180-llcc
25 - qcom,sdm845-llcc
[all …]
|
| /Linux-v5.10/Documentation/xtensa/ |
| D | atomctl.rst | 9 1. With and without an Coherent Cache Controller which
12 2. With and without An Intelligent Memory Controller which
15 The Core comes up with a default value of for the three types of cache ops::
19 On the FPGA Cards we typically simulate an Intelligent Memory controller
21 Memory controller we let it to the atomic operations internally while
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, thought non-MX controlers likely
29 CUSTOMER-WARNING:
35 with the cache being bypassed; for example studying cache alias problems.
[all …]
|
