1# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Last Level Cache Controller
8
9maintainers:
10  - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
12
13description: |
14  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
15  that can be shared by multiple clients. Clients here are different cores in the
16  SoC, the idea is to minimize the local caches at the clients and migrate to
17  common pool of memory. Cache memory is divided into partitions called slices
18  which are assigned to clients. Clients can query the slice details, activate
19  and deactivate them.
20
21properties:
22  compatible:
23    enum:
24      - qcom,sc7180-llcc
25      - qcom,sdm845-llcc
26
27  reg:
28    items:
29      - description: LLCC base register region
30      - description: LLCC broadcast base register region
31
32  reg-names:
33    items:
34      - const: llcc_base
35      - const: llcc_broadcast_base
36
37  interrupts:
38    maxItems: 1
39
40required:
41  - compatible
42  - reg
43  - reg-names
44  - interrupts
45
46additionalProperties: false
47
48examples:
49  - |
50    #include <dt-bindings/interrupt-controller/arm-gic.h>
51
52    system-cache-controller@1100000 {
53      compatible = "qcom,sdm845-llcc";
54      reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
55      reg-names = "llcc_base", "llcc_broadcast_base";
56      interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
57    };
58