Lines Matching +full:cache +full:- +full:controller

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11   - Sagar Kadam <sagar.kadam@sifive.com>
12   - Yash Shah <yash.shah@sifive.com>
13   - Paul Walmsley  <paul.walmsley@sifive.com>
16   The SiFive Level 2 Cache Controller is used to provide access to fast copies
17   of memory for masters in a Core Complex. The Level 2 Cache Controller also
18   acts as directory-based coherency manager.
22   - $ref: /schemas/cache-controller.yaml#
28         - enum:
29             - sifive,fu540-c000-ccache
32     - compatible
37       - const: sifive,fu540-c000-ccache
38       - const: cache
40   cache-block-size:
43   cache-level:
46   cache-sets:
49   cache-size:
52   cache-unified: true
63   next-level-cache: true
65   memory-region:
67       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
68       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
73   - compatible
74   - cache-block-size
75   - cache-level
76   - cache-sets
77   - cache-size
78   - cache-unified
79   - interrupts
80   - reg
83   - |
84     cache-controller@2010000 {
85         compatible = "sifive,fu540-c000-ccache", "cache";
86         cache-block-size = <64>;
87         cache-level = <2>;
88         cache-sets = <1024>;
89         cache-size = <2097152>;
90         cache-unified;
92         interrupt-parent = <&plic0>;
96         next-level-cache = <&L25>;
97         memory-region = <&l2_lim>;