Lines Matching +full:cache +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
208 # ARM1020 - needs validating
222 with an addition of a floating-point unit.
227 # ARM1020E - needs validating
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
260 # ARM1026EJ-S
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
275 Say Y if you want support for the ARM1026EJ-S processor.
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
296 Say Y if you want support for the SA-110 processor.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
521 # The cache model
553 # The copy-page model
573 ARM Architecture Version 4 TLB with writethrough cache.
578 ARM Architecture Version 4 TLB with writeback cache.
583 ARM Architecture Version 4 TLB with writeback cache and invalidate
584 instruction cache entry.
589 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
594 Faraday ARM FA526 architecture, unified TLB with writeback cache
595 and invalidate instruction cache entry. Branch target buffer is
612 tag TLB and possibly cache entries.
649 interrupts supported by the NVIC on Cortex-M family.
654 # CPU supports 36-bit I/O
709 Extensions to install hypervisors without run-time firmware
744 bool "Build big-endian kernel"
747 Say Y if you plan on running a kernel in big-endian mode.
749 port must properly enable any big-endian related features
757 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
764 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
778 bool "Disable I-Cache (I-bit)"
781 Say Y here to disable the processor instruction cache. Unless
785 bool "Workaround for I-Cache line size mismatch between CPU cores"
788 Some big.LITTLE systems have I-Cache line size mismatch between
790 proper I-Cache support on such systems. If unsure, say N.
793 bool "Disable D-Cache (C-bit)"
796 Say Y here to disable the processor data cache. Unless
803 default 0x00002000 # default size for ARM946E-S
805 Some cores are synthesizable to have various sized cache. For
806 ARM946E-S case, it can vary from 0KB to 1MB.
807 To support such cache operations, it is efficient to know the size
813 bool "Force write through D-cache"
817 Say Y here to use the data cache in writethrough mode. Unless you
821 bool "Round robin I and D cache replacement algorithm"
824 Say Y here to use the predictable round-robin cache replacement
841 Speculation attacks against some high-performance processors rely
848 This config option will take CPU-specific actions to harden
859 An SMP system using a pre-ARMv6 processor (there are apparently
913 bool "Enable read/write for ownership DMA cache maintenance"
918 cache maintenance operations and the dma_{map,unmap}_area()
919 functions may leave stale cache entries on other CPUs. By
921 DMA cache maintenance functions is performed. These LDR/STR
922 instructions change the cache line state to shared or modified
923 so that the cache operation has the desired effect.
926 not perform speculative loads into the D-cache. For such
927 processors, if cache maintenance operations are not broadcast
928 in hardware, other workarounds are needed (e.g. cache
938 The outer cache has a outer_cache_fns.sync function pointer
939 that can be used to drain the write buffer of the outer cache.
942 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
946 This option enables the Broadcom Brahma-B15 read-ahead cache
947 controller. If disabled, the read-ahead cache remains off.
950 bool "Enable the Feroceon L2 cache controller"
955 This option enables the Feroceon L2 cache controller.
958 bool "Force Feroceon L2 cache write through"
961 Say Y here to use the Feroceon L2 cache in writethrough mode.
968 or PL310 cache controller, but where its use is optional.
973 Boards or SoCs which always require the cache controller
979 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
991 of the L220 and PL310 outer cache controllers.
998 The PL310 L2 cache controller implements three types of Clean &
1010 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1019 bool "PL310 errata: cache sync operation may be faulty"
1023 Under some condition the effect of cache sync operation on
1027 is to replace the normal offset of cache sync operation (0x730)
1029 This has the same effect as the cache sync operation: store buffer
1036 not automatically drain. This can cause normal, non-cacheable
1040 on systems with an outer cache, the store buffer is drained
1046 bool "Enable the Tauros2 L2 cache controller"
1051 This option enables the Tauros2 L2 cache controller (as
1055 bool "Enable the UniPhier outer cache controller"
1061 This option enables the UniPhier outer cache (system cache)
1062 controller.
1065 bool "Enable the L2 cache on XScale3"
1070 This option enables the L2 cache on XScale3.
1076 Setting ARM L1 cache line size to 64 Bytes.
1081 Setting ARM L1 cache line size to 128 Bytes.
1090 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1106 On some of the beefier ARMv7-M machines (with DMA and write
1122 bool "Make rodata strictly non-executable"
1126 If this is set, rodata will be made explicitly non-executable. This
1129 additional section-aligned split of rodata from kernel text so it
1130 can be made explicitly non-executable. This padding may waste memory