Lines Matching +full:cache +full:- +full:controller
23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
40 /* Primary interrupt controller in the test chip */
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
44 #address-cells = <1>;
45 interrupt-controller;
50 /* Secondary interrupt controller on the FPGA */
51 intc_second: interrupt-controller@10040000 {
53 #interrupt-cells = <3>;
54 #address-cells = <1>;
55 interrupt-controller;
58 interrupt-parent = <&intc>;
62 L2: cache-controller {
63 compatible = "arm,l220-cache";
65 interrupt-parent = <&intc>;
69 cache-unified;
70 cache-level = <2>;
72 * Override default cache size, sets and
76 * cache to hang unless disabled.
78 cache-size = <1048576>; // 1MB
79 cache-sets = <4096>;
80 cache-line-size = <32>;
81 arm,shared-override;
82 arm,parity-enable;
83 arm,outer-sync-disable;
87 compatible = "arm,arm11mp-scu";
92 compatible = "arm,arm11mp-twd-timer";
94 interrupt-parent = <&intc>;
99 compatible = "arm,arm11mp-twd-wdt";
101 interrupt-parent = <&intc>;
107 compatible = "arm,arm11mpcore-pmu";
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
144 interrupt-parent = <&intc>;
149 interrupt-parent = <&intc>;
154 interrupt-parent = <&intc>;
159 interrupt-parent = <&intc>;
164 interrupt-parent = <&intc>;
169 interrupt-parent = <&intc>;
174 interrupt-parent = <&intc>;
184 interrupt-parent = <&intc_second>;
189 interrupt-parent = <&intc_second>;
194 interrupt-parent = <&intc_second>;
199 interrupt-parent = <&intc_second>;
205 interrupt-parent = <&intc_second>;
211 interrupt-parent = <&intc_second>;
217 interrupt-parent = <&intc_second>;