Lines Matching +full:cache +full:- +full:controller

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include "fsl-ls208xa.dtsi"
17 		compatible = "arm,cortex-a72";
20 		cpu-idle-states = <&CPU_PW20>;
21 		next-level-cache = <&cluster0_l2>;
22 		#cooling-cells = <2>;
27 		compatible = "arm,cortex-a72";
30 		cpu-idle-states = <&CPU_PW20>;
31 		next-level-cache = <&cluster0_l2>;
32 		#cooling-cells = <2>;
37 		compatible = "arm,cortex-a72";
40 		cpu-idle-states = <&CPU_PW20>;
41 		next-level-cache = <&cluster1_l2>;
42 		#cooling-cells = <2>;
47 		compatible = "arm,cortex-a72";
50 		cpu-idle-states = <&CPU_PW20>;
51 		next-level-cache = <&cluster1_l2>;
52 		#cooling-cells = <2>;
57 		compatible = "arm,cortex-a72";
60 		next-level-cache = <&cluster2_l2>;
61 		cpu-idle-states = <&CPU_PW20>;
62 		#cooling-cells = <2>;
67 		compatible = "arm,cortex-a72";
70 		cpu-idle-states = <&CPU_PW20>;
71 		next-level-cache = <&cluster2_l2>;
72 		#cooling-cells = <2>;
77 		compatible = "arm,cortex-a72";
80 		cpu-idle-states = <&CPU_PW20>;
81 		next-level-cache = <&cluster3_l2>;
82 		#cooling-cells = <2>;
87 		compatible = "arm,cortex-a72";
90 		cpu-idle-states = <&CPU_PW20>;
91 		next-level-cache = <&cluster3_l2>;
92 		#cooling-cells = <2>;
95 	cluster0_l2: l2-cache0 {
96 		compatible = "cache";
99 	cluster1_l2: l2-cache1 {
100 		compatible = "cache";
103 	cluster2_l2: l2-cache2 {
104 		compatible = "cache";
107 	cluster3_l2: l2-cache3 {
108 		compatible = "cache";
111 	CPU_PW20: cpu-pw20 {
112 		compatible = "arm,idle-state";
113 		idle-state-name = "PW20";
114 		arm,psci-suspend-param = <0x0>;
115 		entry-latency-us = <2000>;
116 		exit-latency-us = <2000>;
117 		min-residency-us = <6000>;
122 	compatible = "fsl,ls2088a-pcie";
123 	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
131 	compatible = "fsl,ls2088a-pcie";
132 	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
140 	compatible = "fsl,ls2088a-pcie";
141 	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
149 	compatible = "fsl,ls2088a-pcie";
150 	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */