Lines Matching +full:cache +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
17 common pool of memory. Cache memory is divided into partitions called slices
24 - qcom,sc7180-llcc
25 - qcom,sdm845-llcc
29 - description: LLCC base register region
30 - description: LLCC broadcast base register region
32 reg-names:
34 - const: llcc_base
35 - const: llcc_broadcast_base
41 - compatible
42 - reg
43 - reg-names
44 - interrupts
49 - |
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 system-cache-controller@1100000 {
53 compatible = "qcom,sdm845-llcc";
55 reg-names = "llcc_base", "llcc_broadcast_base";