Lines Matching +full:cache +full:- +full:controller
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
68 It should be noticed that keeping both GHES and a hardware-driven
93 When enabled, in each of the respective memory controller directories
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
104 tristate "Amazon's Annapurna Lab Memory Controller"
172 E3-1200 based DRAM controllers.
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
233 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
248 system has non-volatile DIMMs you should also manually
260 system has non-volatile DIMMs you should also manually
268 Pondicherry2 Integrated Memory Controller. This SoC IP is
270 micro-server but may appear on others in the future.
301 tristate "Cell Broadband Engine memory controller"
305 Cell Broadband Engine internal memory controller
309 tristate "PPC4xx IBM DDR2 Memory Controller"
313 with the IBM DDR2 memory controller found in various
318 tristate "AMD8131 HyperTransport PCI-X Tunnel"
322 AMD8131 HyperTransport PCI-X Tunnel chip.
336 tristate "IBM CPC925 Memory Controller (PPC970FX)"
340 IBM CPC925 Bridge and Memory Controller, which is
345 tristate "Highbank Memory Controller"
349 Calxeda Highbank memory controller.
352 tristate "Highbank L2 Cache"
356 Calxeda Highbank memory controller.
373 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
380 tristate "Cavium Octeon PCI Controller"
392 Cavium ThunderX memory controllers (LMC), Cache
393 Coherent Processor Interconnect (CCPI) and L2 cache
414 bool "Altera L2 Cache ECC"
418 Altera L2 cache Memory for Altera SoCs. This option
419 requires L2 cache.
422 bool "Altera On-Chip RAM ECC"
426 Altera On-Chip RAM Memory for Altera SoCs.
477 bool "Marvell Armada XP DDR and L2 Cache ECC"
481 DDR RAM and L2 cache controllers.
484 tristate "Synopsys DDR Memory Controller"
488 memory controller.
491 tristate "APM X-Gene SoC"
495 APM X-Gene family of SOCs.
498 tristate "Texas Instruments DDR3 ECC Controller"
504 tristate "QCOM EDAC Controller"
511 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
534 tristate "ARM DMC-520 ECC"
538 SoCs with ARM DMC-520 DRAM controller.