| /Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
20 …escription": "The number of 64 byte instruction cache line fulfilled from system memory or another…
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
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| D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
44 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
50 "BriefDescription": "L1 Cache evictions for dirty data"
54 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
60 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
86 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m…
6 "BriefDescription": "L1 instruction cache refill"
9 …LB refill. This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes r…
15 …"PublicDescription": "L1 data cache refill. This event counts any load or store operation or page …
18 "BriefDescription": "L1 data cache refill"
21 …tion": "L1 data cache access. This event counts any load or store operation or page table walk acc…
24 "BriefDescription": "L1 data cache access"
27 … data TLB refill. This event counts any refill of the data L1 TLB from the L2 TLB. This includes r…
33 …on cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which ac…
36 "BriefDescription": "L1 instruction cache access"
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
12 "BriefDescription": "L2 cache request misses"
16 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
24 "BriefDescription": "L2 cache requests"
28 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
52 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
60 "BriefDescription": "L1 Cache evictions for dirty data"
64 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
72 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
101 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
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| /Linux-v5.10/arch/powerpc/sysdev/ |
| D | fsl_85xx_l2ctlr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
5 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
27 return -EINVAL; in get_cache_sram_params()
30 return -EINVAL; in get_cache_sram_params()
32 sram_params->sram_offset = addr; in get_cache_sram_params()
33 sram_params->sram_size = size; in get_cache_sram_params()
56 __setup("cache-sram-size=", get_size_from_cmdline);
57 __setup("cache-sram-offset=", get_offset_from_cmdline);
68 if (!dev->dev.of_node) { in mpc85xx_l2ctlr_of_probe()
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| /Linux-v5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
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| D | frontend.json | 47 "BriefDescription": "Number of I-ERAT reloads",
89 …fDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another…
90 …cDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another…
95 …efDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another …
96 …icDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another …
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 5 "BriefDescription": "Demand Data Read miss L2, no rejects",
8 …": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejecte…
15 "BriefDescription": "RFO requests that miss L2 cache.",
24 "BriefDescription": "L2 cache misses when fetching instructions.",
33 "BriefDescription": "Demand requests that miss L2 cache.",
42 "BriefDescription": "L2 prefetch requests that miss L2 cache",
45 …n": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.…
52 "BriefDescription": "All requests that miss L2 cache.",
61 "BriefDescription": "Demand Data Read requests that hit L2 cache",
64 …n": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejecte…
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | cache.json | 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/haswell/ |
| D | cache.json | 3 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
10 "BriefDescription": "Demand Data Read miss L2, no rejects",
14 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
20 "BriefDescription": "RFO requests that miss L2 cache",
24 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
30 "BriefDescription": "L2 cache misses when fetching instructions",
34 "PublicDescription": "Demand requests that miss L2 cache.",
41 "BriefDescription": "Demand requests that miss L2 cache",
45 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
51 "BriefDescription": "L2 prefetch requests that miss L2 cache",
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| /Linux-v5.10/arch/mips/include/asm/octeon/ |
| D | cvmx-l2c.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
42 /* Based on 128 byte cache line size */
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
159 * Configure one of the four L2 Cache performance counters to capture event
163 * @event: The type of L2 Cache event occurrence to count.
173 * Read the given L2 Cache performance counter. The counter must be configured
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | cache.json | 5 "BriefDescription": "Demand Data Read miss L2, no rejects",
9 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
16 "BriefDescription": "RFO requests that miss L2 cache",
19 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
26 "BriefDescription": "L2 cache misses when fetching instructions",
29 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
36 "BriefDescription": "Demand requests that miss L2 cache",
40 "PublicDescription": "Demand requests that miss L2 cache.",
47 "BriefDescription": "L2 prefetch requests that miss L2 cache",
50 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/icelake/ |
| D | cache.json | 4 …"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not …
11 "BriefDescription": "Demand Data Read miss L2, no rejects"
15 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
22 "BriefDescription": "RFO requests that miss L2 cache"
26 "PublicDescription": "Counts L2 cache misses when fetching instructions.",
33 "BriefDescription": "L2 cache misses when fetching instructions"
37 "PublicDescription": "Counts demand requests that miss L2 cache.",
44 "BriefDescription": "Demand requests that miss L2 cache"
48 …"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event account…
55 "BriefDescription": "SW prefetch requests that miss L2 cache."
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | cache.json | 5 "BriefDescription": "Demand Data Read miss L2, no rejects",
8 …": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejecte…
15 "BriefDescription": "RFO requests that miss L2 cache.",
24 "BriefDescription": "L2 cache misses when fetching instructions.",
33 "BriefDescription": "Demand requests that miss L2 cache.",
42 "BriefDescription": "L2 prefetch requests that miss L2 cache",
45 …n": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.…
52 "BriefDescription": "All requests that miss L2 cache.",
61 "BriefDescription": "Demand Data Read requests that hit L2 cache",
64 …ounts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | cache.json | 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
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| /Linux-v5.10/arch/arm/mm/ |
| D | cache-feroceon-l2.c | 2 * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
11 * - Unified Layer 2 Cache for Feroceon CPU Cores,
12 * Document ID MV-S104858-00, Rev. A, October 23 2007.
22 #include <asm/hardware/cache-feroceon-l2.h>
27 * Low-level cache maintenance operations.
29 * As well as the regular 'clean/invalidate/flush L2 cache line by
30 * MVA' instructions, the Feroceon L2 cache controller also features
31 * 'clean/invalidate L2 range by MVA' operations.
33 * Cache range operations are initiated by writing the start and
35 * cache line whose first byte address lies in the inclusive range
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| /Linux-v5.10/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | marked.json | 10 … level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/di…
25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
30 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem…
35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp…
45 …": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. Th…
50 …": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. Th…
60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
80 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c…
85 …"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
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| /Linux-v5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
32 "freq-domain0", "freq-domain1".
34 - #freq-domain-cells:
38 * Property qcom,freq-domain
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| /Linux-v5.10/arch/mips/cavium-octeon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
11 non-CN63XXP1 hardware, so it is recommended to select "n"
15 int "Number of L1 cache lines reserved for CVMSEG memory"
20 local memory; the larger CVMSEG is, the smaller the cache is.
21 This selects the size of CVMSEG LM, which is in cache blocks. The
22 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
30 bool "Lock often used kernel code in the L2"
33 Enable locking parts of the kernel into the L2 cache.
36 bool "Lock the TLB handler in L2"
40 Lock the low level TLB fast path into L2.
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | cache.json | 3 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
9 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ"
12 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
21 …his event counts requests originating from the core that references a cache line in the L2 cache.",
27 "BriefDescription": "L2 cache requests from this core"
30 …Description": "This event counts the total number of L2 cache references and the number of L2 cach…
36 "BriefDescription": "L2 cache request misses"
39 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
45 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
67 …"PublicDescription": "This event counts the number of retire stores that experienced cache line bo…
[all …]
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