Lines Matching +full:l2 +full:- +full:cache

4 …"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not …
11         "BriefDescription": "Demand Data Read miss L2, no rejects"
15         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
22         "BriefDescription": "RFO requests that miss L2 cache"
26         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
33         "BriefDescription": "L2 cache misses when fetching instructions"
37         "PublicDescription": "Counts demand requests that miss L2 cache.",
44         "BriefDescription": "Demand requests that miss L2 cache"
48 …"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event account…
55         "BriefDescription": "SW prefetch requests that miss L2 cache."
59 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
66         "BriefDescription": "Demand Data Read requests that hit L2 cache"
70         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
77         "BriefDescription": "RFO requests that hit L2 cache"
81         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
88         "BriefDescription": "L2 cache hits when fetching instructions, code reads."
92 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts…
99         "BriefDescription": "SW prefetch requests that hit L2 cache."
103 …ng requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejecte…
114 …on": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests in…
121         "BriefDescription": "RFO requests to L2 cache"
125         "PublicDescription": "Counts the total number of L2 code requests.",
132         "BriefDescription": "L2 code requests"
136         "PublicDescription": "Counts demand requests to L2 cache.",
143         "BriefDescription": "Demand requests to L2 cache"
147 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
194 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
201 …escription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources."
205 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
212         "BriefDescription": "Counts the number of cache lines replaced in L1 data cache."
216 …y cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sendi…
228 …o be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor…
239 …o be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor…
273 …d prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 …
390 …s retired load instructions with at least one uop that hit in the L1 data cache. This event includ…
397         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
403         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
410         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
416 …icDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
423         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
429 …escription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
436         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
442         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
449         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
455 …escription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
462         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
468 … missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not…
481 …oad instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
488 …oad instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
494 …ired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
501 …tired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
532 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
539         "BriefDescription": "L2 cache lines filling L2"