Lines Matching +full:l2 +full:- +full:cache

1 # SPDX-License-Identifier: GPL-2.0
11 	  non-CN63XXP1 hardware, so it is recommended to select "n"
15 	int "Number of L1 cache lines reserved for CVMSEG memory"
20 	  local memory; the larger CVMSEG is, the smaller the cache is.
21 	  This selects the size of CVMSEG LM, which is in cache blocks. The
22 	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
30 	bool "Lock often used kernel code in the L2"
33 	  Enable locking parts of the kernel into the L2 cache.
36 	bool "Lock the TLB handler in L2"
40 	  Lock the low level TLB fast path into L2.
43 	bool "Lock the exception handler in L2"
47 	  Lock the low level exception handler into L2.
50 	bool "Lock the interrupt handler in L2"
54 	  Lock the low level interrupt handler into L2.
57 	bool "Lock the 2nd level interrupt handler in L2"
61 	  Lock the 2nd level interrupt handler in L2.
64 	bool "Lock memcpy() in L2"
68 	  Lock the kernel's implementation of memcpy() into L2.
77 	  will be called octeon-ilm