Lines Matching +full:l2 +full:- +full:cache

5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
20 …escription": "The number of 64 byte instruction cache line fulfilled from system memory or another…
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30     "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
111 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
134     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
140 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
146     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
152 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-…
158 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
164     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
170     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
176 …"BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divide…
182 …"BriefDescription": "LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining …
188 …"BriefDescription": "LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining …
194 …"BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write …
200 …"BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Wri…
206 …BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data c…
212 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
218 …fDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache…
224 …Description": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache …
230 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
236 …Description": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction…
242 …efDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instructi…
248 …iefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruct…
254 …BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instru…
260 …"Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request…
266 … "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache reques…
272 …ription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in …
278     "BriefDescription": "L2 prefetch hit in L2.",
284 …"BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipelin…
290 …"BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline whi…
296     "BriefDescription": "Caching: L3 cache accesses",
317     "BriefDescription": "L3 cache misses",
324 …"BriefDescription": "L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignor…