Lines Matching +full:l2 +full:- +full:cache
3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
23 "PublicDescription": "RFO requests that hit L2 cache.",
29 "BriefDescription": "RFO requests that hit L2 cache",
33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
39 "BriefDescription": "RFO requests that miss L2 cache",
43 "PublicDescription": "Counts all L2 store RFO requests.",
49 "BriefDescription": "RFO requests to L2 cache",
53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
59 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
63 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
69 "BriefDescription": "L2 cache misses when fetching instructions",
73 "PublicDescription": "Counts all L2 code requests.",
79 "BriefDescription": "L2 code requests",
83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
89 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
93 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
99 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
103 "PublicDescription": "Counts all L2 HW prefetcher requests.",
109 "BriefDescription": "Requests from L2 hardware prefetchers",
113 "PublicDescription": "RFOs that miss cache lines.",
119 "BriefDescription": "RFOs that miss cache lines",
123 "PublicDescription": "RFOs that hit cache lines in M state.",
129 "BriefDescription": "RFOs that hit cache lines in M state",
133 "PublicDescription": "RFOs that access cache lines in any state.",
139 "BriefDescription": "RFOs that access cache lines in any state",
149 …iption": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from…
153 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
159 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
163 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
169 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
178 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
182 …"PublicDescription": "This event counts each cache miss condition for references to the last level…
188 "BriefDescription": "Core-originated cacheable demand requests missed LLC",
192 …nt counts requests originating from the core that reference a cache line in the last level cache.",
198 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
245 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
486 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
496 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
516 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
526 "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
536 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
546 …ces were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not…
556 …tired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
566 …": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
590 …"PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not…
600 "PublicDescription": "Demand Data Read requests that access L2 cache.",
606 "BriefDescription": "Demand Data Read requests that access L2 cache",
610 "PublicDescription": "RFO requests that access L2 cache.",
616 "BriefDescription": "RFO requests that access L2 cache",
620 "PublicDescription": "L2 cache accesses when fetching instructions.",
626 "BriefDescription": "L2 cache accesses when fetching instructions",
630 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
636 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
640 "PublicDescription": "L1D writebacks that access L2 cache.",
646 "BriefDescription": "L1D writebacks that access L2 cache",
650 "PublicDescription": "L2 fill requests that access L2 cache.",
656 "BriefDescription": "L2 fill requests that access L2 cache",
660 "PublicDescription": "L2 writebacks that access L2 cache.",
666 "BriefDescription": "L2 writebacks that access L2 cache",
670 "PublicDescription": "Transactions accessing L2 pipe.",
676 "BriefDescription": "Transactions accessing L2 pipe",
680 "PublicDescription": "L2 cache lines in I state filling L2.",
686 "BriefDescription": "L2 cache lines in I state filling L2",
690 "PublicDescription": "L2 cache lines in S state filling L2.",
696 "BriefDescription": "L2 cache lines in S state filling L2",
700 "PublicDescription": "L2 cache lines in E state filling L2.",
706 "BriefDescription": "L2 cache lines in E state filling L2",
710 "PublicDescription": "L2 cache lines filling L2.",
716 "BriefDescription": "L2 cache lines filling L2",
720 "PublicDescription": "Clean L2 cache lines evicted by demand.",
726 "BriefDescription": "Clean L2 cache lines evicted by demand",
730 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
736 "BriefDescription": "Dirty L2 cache lines evicted by demand",
740 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
746 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
750 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
756 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
760 "PublicDescription": "Dirty L2 cache lines filling the L2.",
766 "BriefDescription": "Dirty L2 cache lines filling the L2",
799 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
847 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
871 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
907 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
955 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
991 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
1003 …t include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to…
1015 … "Counts requests where the address of an atomic lock instruction spans a cache line boundary or t…
1027 "BriefDescription": "Counts non-temporal stores",