Lines Matching +full:l2 +full:- +full:cache
5 "BriefDescription": "Demand Data Read miss L2, no rejects",
8 …": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejecte…
15 "BriefDescription": "RFO requests that miss L2 cache.",
24 "BriefDescription": "L2 cache misses when fetching instructions.",
33 "BriefDescription": "Demand requests that miss L2 cache.",
42 "BriefDescription": "L2 prefetch requests that miss L2 cache",
45 …n": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.…
52 "BriefDescription": "All requests that miss L2 cache.",
61 "BriefDescription": "Demand Data Read requests that hit L2 cache",
64 …ounts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
71 "BriefDescription": "RFO requests that hit L2 cache.",
80 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
89 "BriefDescription": "L2 prefetch requests that hit L2 cache",
92 …on": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache.…
102 …ng requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejecte…
109 "BriefDescription": "RFO requests to L2 cache",
112 …event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests in…
119 "BriefDescription": "L2 code requests",
122 "PublicDescription": "This event counts the total number of L2 code requests.",
129 "BriefDescription": "Demand requests to L2 cache.",
138 "BriefDescription": "Requests from L2 hardware prefetchers",
141 …"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetch…
148 "BriefDescription": "All L2 requests.",
157 "BriefDescription": "Not rejected writebacks that hit L2 cache",
160 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
167 "BriefDescription": "Core-originated cacheable demand requests missed L3",
170 …ublicDescription": "This event counts core-originated cacheable demand requests that miss the last…
177 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
180 …licDescription": "This event counts core-originated cacheable demand requests that refer to the la…
190 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
232 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
243 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
255 …o be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor…
277 …ery cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sendi…
288 …o be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor…
300 …ery cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sendi…
311 …o be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor…
323 …o be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor…
373 …and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 …
442 …ription": "This event counts line-splitted load uops retired to the architected path. A line split…
454 …ription": "This event counts line-splitted store uops retired to the architected path. A line spli…
467 … a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memo…
479 … a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memo…
487 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
492 …-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even thoug…
499 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
505 …": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.",
518 …unts retired load uops which data sources were data hits in the last-level (L3) cache without snoo…
525 "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
530 …unts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting ex…
537 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
542 …t counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting ex…
549 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
561 …ces were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not…
566 …cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-2…
573 …etired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
579 …ed load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache…
586 …n": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
592 …red load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.",
618 …nt counts retired load uops which data sources were hits in the last-level (L3) cache without snoo…
650 "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
662 "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
674 "BriefDescription": "Demand Data Read requests that access L2 cache",
677 …"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including …
684 "BriefDescription": "RFO requests that access L2 cache",
687 … "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
694 "BriefDescription": "L2 cache accesses when fetching instructions",
697 …"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions…
704 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
707 …"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including reje…
714 "BriefDescription": "L1D writebacks that access L2 cache",
717 "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
724 "BriefDescription": "L2 fill requests that access L2 cache",
727 "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
734 "BriefDescription": "L2 writebacks that access L2 cache",
737 "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
744 "BriefDescription": "Transactions accessing L2 pipe",
747 …"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pag…
754 "BriefDescription": "L2 cache lines in I state filling L2",
757 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
764 "BriefDescription": "L2 cache lines in S state filling L2",
767 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
774 "BriefDescription": "L2 cache lines in E state filling L2",
777 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
784 "BriefDescription": "L2 cache lines filling L2",
787 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
794 "BriefDescription": "Clean L2 cache lines evicted by demand.",