Lines Matching +full:l2 +full:- +full:cache

4     "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12     "BriefDescription": "All L1 Data Cache Accesses",
17     "BriefDescription": "All L2 Cache Accesses",
24     "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30     "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35     "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41     "BriefDescription": "All L2 Cache Misses",
48     "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54     "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59     "BriefDescription": "L2 Cache Misses from L2 HWPF",
65     "BriefDescription": "All L2 Cache Hits",
72     "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78     "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
83     "BriefDescription": "L2 Cache Hits from L2 HWPF",
110     "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
124     "BriefDescription": "L2 ITLB Misses & Instruction page walks",
136     "BriefDescription": "L2 DTLB Misses & Data page walks",
148     "BriefDescription": "Micro-ops Dispatched",
160     "BriefDescription": "Micro-ops Retired"
168     "ScaleUnit": "3e-5MiB"
172 …roximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
176     "ScaleUnit": "6.1e-5MiB"