Searched refs:main (Results 1876 – 1900 of 1972) sorted by relevance
1...<<717273747576777879
| /Zephyr-latest/doc/services/sensing/ |
| D | index.rst | 81 * single thread main loop for all sensor objects sampling and process.
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| /Zephyr-latest/boards/st/stm32h7b3i_dk/doc/ |
| D | index.rst | 178 as well as by the main PLL clock. By default, the System clock is driven
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| /Zephyr-latest/boards/st/stm32h7s78_dk/doc/ |
| D | index.rst | 223 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/nucleo_h755zi_q/doc/ |
| D | index.rst | 132 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/boards/st/nucleo_u083rc/doc/ |
| D | index.rst | 212 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/nucleo_u575zi_q/doc/ |
| D | index.rst | 221 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/nucleo_wba52cg/doc/ |
| D | nucleo_wba52cg.rst | 206 as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz.
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| /Zephyr-latest/boards/st/stm32h745i_disco/doc/ |
| D | index.rst | 119 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | r7fa6m5xh.dtsi | 286 xtal: clock-main-osc {
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| /Zephyr-latest/tests/bsim/bluetooth/ll/cis/src/ |
| D | main.c | 868 int main(void) function
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| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/hci_test_app/src/ |
| D | main.c | 758 int main(void) in main() function
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| /Zephyr-latest/tests/cmake/yaml/ |
| D | CMakeLists.txt | 405 target_sources(app PRIVATE src/main.c)
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| /Zephyr-latest/scripts/ci/ |
| D | check_compliance.py | 1924 def main(argv=None): function
1963 main(sys.argv[1:])
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| /Zephyr-latest/doc/develop/flash_debug/ |
| D | host-tools.rst | 282 will need to add a breakpoint at ``main`` or the reset handler manually.
546 https://github.com/pyocd/pyOCD/tree/main/pyocd/target/builtin
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| /Zephyr-latest/doc/hardware/pinctrl/ |
| D | index.rst | 14 controllers**. The pin controller's main users are SoC hardware peripherals,
60 Therefore, the main users of the pin control driver are SoC peripherals. In
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| /Zephyr-latest/boards/espressif/esp32_ethernet_kit/doc/ |
| D | index.rst | 41 The block diagram below shows the main components of ESP32-Ethernet-Kit
147 power supply for the Ethernet Board (A). The main components of the PoE Board
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| /Zephyr-latest/boards/snps/emsdp/doc/ |
| D | index.rst | 245 (gdb) b main
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| /Zephyr-latest/boards/st/nucleo_h745zi_q/doc/ |
| D | index.rst | 144 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/boards/st/nucleo_l552ze_q/doc/ |
| D | nucleol552ze_q.rst | 265 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/nucleo_wl55jc/doc/ |
| D | nucleo_wl55jc.rst | 240 as well as main PLL clock. By default System clock is driven by HSE clock at
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| /Zephyr-latest/samples/net/lwm2m_client/ |
| D | README.rst | 270 [lwm2m-client] [INF] main: Run LWM2M client
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| /Zephyr-latest/boards/adi/max78002evkit/doc/ |
| D | index.rst | 173 | JP2 | 3V3 SW PM BYPASS | Power monitor shunts for main 3.3 V system power are bypassed …
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| /Zephyr-latest/boards/cypress/cy8ckit_062_ble/doc/ |
| D | index.rst | 70 34. Cypress main voltage regulator (MB39C022G, U6)
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| /Zephyr-latest/boards/nordic/nrf5340dk/doc/ |
| D | index.rst | 59 the slow clock is 32.768 kHz. The frequency of the main clock
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| /Zephyr-latest/tests/benchmarks/mbedtls/src/ |
| D | benchmark.c | 288 int main(void) in main() function
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