1.. zephyr:board:: max78002evkit 2 3Overview 4******** 5The MAX78002 evaluation kit (EV kit) provides a platform and tools for leveraging device capabilities to build new 6generations of artificial intelligence (AI) products. 7 8The kit provides optimal versatility with a modular peripheral architecture, allowing a variety of input and output 9devices to be remotely located. DVP and CSI cameras, I2S audio peripherals, digital microphones, and analog sensors 10are supported, while a pair of industry-standard QWIIC connectors supports a large and growing array of aftermarket 11development boards. An onboard stereo audio codec offers line-level audio input and output, and tactile input is 12provided by a touch-enabled 2.4in TFT display. The MAX78002 energy consumption is tracked by a power accumulator, 13with four channels of formatted results presented on a secondary TFT display. All device GPIOs are accessible on 140.1in pin headers. A standard coaxial power jack serves as power input, using the included 5V, 3A wall-mount 15adapter. Two USB connectors provide serial access to the MAX78002, one directly and the other through a USB to UART 16bridge. A third USB connector allows access to the MAX78002 energy consumption data. Rounding out the features, a 17microSD connector provides the capability for inexpensive highdensity portable data storage. 18 19The Zephyr port is running on the MAX78002 MCU. 20 21.. image:: img/max78002evkit.webp 22 :align: center 23 :alt: MAX78002 EVKIT Front 24 25.. image:: img/max78002evkit_back.webp 26 :align: center 27 :alt: MAX78002 EVKIT Back 28 29Hardware 30******** 31 32- MAX78002 MCU: 33 34 - Dual-Core, Low-Power Microcontroller 35 36 - Arm Cortex-M4 Processor with FPU up to 120MHz 37 - 2.5MB Flash, 64KB ROM, and 384KB SRAM 38 - Optimized Performance with 16KB Instruction Cache 39 - Optional Error Correction Code (ECC SEC-DED) for SRAM 40 - 32-Bit RISC-V Coprocessor up to 60MHz 41 - Up to 60 General-Purpose I/O Pins 42 - MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller V2.1 43 - Support for Two Data Lanes 44 - 12-Bit Parallel Camera Interface 45 - I 2S Controller/Target for Digital Audio Interface 46 - Secure Digital Interface Supports SD 3.0/SDIO 3.0/eMMC 4.51 47 48 - Convolutional Neural Network (CNN) Accelerator 49 50 - Highly Optimized for Deep CNNs 51 - 2 Million 8-Bit Weight Capacity with 1-, 2-, 4-, and 8-bit Weights 52 - 1.3MB CNN Data Memory 53 - Programmable Input Image Size up to 2048 x 2048 Pixels 54 - Programmable Network Depth up to 128 Layers 55 - Programmable per Layer Network Channel Widths up to 1024 Channels 56 - 1- and 2-Dimensional Convolution Processing 57 - Capable of Processing VGA Images at 30fps 58 59 - Power Management for Extending Battery Life 60 61 - Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS) 62 - 2.85V to 3.6V Supply Voltage Range 63 - Support of Optional External Auxiliary CNN Power Supply 64 - Dynamic Voltage Scaling Minimizes Active Core Power Consumption 65 - 23.9μA/MHz While Loop Execution at 3.3V from Cache (CM4 only) 66 - Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled 67 68 - Security and Integrity 69 70 - Available Secure Boot 71 - AES 128/192/256 Hardware Acceleration Engine 72 - True Random Number Generator (TRNG) Seed Generator 73 74 - Ultra-Low-Power Wireless Microcontroller 75 76 - Internal 100MHz Oscillator 77 - Flexible Low-Power Modes with 7.3728MHz System Clock Option 78 - 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank) 79 - 16KB Instruction Cache 80 81 - Bluetooth 5.2 LE Radio 82 83 - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing 84 - Fully Open-Source Bluetooth 5.2 Stack Available 85 - Supports AoA, AoD, LE Audio, and Mesh 86 - High-Throughput (2Mbps) Mode 87 - Long-Range (125kbps and 500kbps) Modes 88 - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm 89 - Single-Ended Antenna Connection (50Ω) 90 91 - Power Management Maximizes Battery Life 92 93 - 2.0V to 3.6V Supply Voltage Range 94 - Integrated SIMO Power Regulator 95 - Dynamic Voltage Scaling (DVS) 96 - 23.8μA/MHz Active Current at 3.0V 97 - 4.4μA at 3.0V Retention Current for 32KB 98 - Selectable SRAM Retention + RTC in Low-Power Modes 99 100 - Multiple Peripherals for System Control 101 102 - Up to Two High-Speed SPI Master/Slave 103 - Up to Three High-Speed I2C Master/Slave (3.4Mbps) 104 - Up to Four UART, One I2S Master/Slave 105 - Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps 106 - Up to Four Micro-Power Comparators 107 - Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers 108 - 1-Wire® Master 109 - Up to Four Pulse Train (PWM) Engines 110 - RTC with Wake-Up Timer 111 - Up to 52 GPIOs 112 113 - Security and Integrity 114 115 - Available Secure Boot 116 - TRNG Seed Generator 117 - AES 128/192/256 Hardware Acceleration Engine 118 119- External devices connected to the MAX78002 EVKIT: 120 121 - Color TFT Display 122 - Audio Stereo Codec Interface 123 - Digital Microphone 124 - A 8Mb QSPI ram 125 126Supported Features 127================== 128 129The ``max78002evkit/max78002/m4`` board target supports the following interfaces: 130 131+-----------+------------+-------------------------------------+ 132| Interface | Controller | Driver/Component | 133+===========+============+=====================================+ 134| NVIC | on-chip | nested vector interrupt controller | 135+-----------+------------+-------------------------------------+ 136| SYSTICK | on-chip | systick | 137+-----------+------------+-------------------------------------+ 138| CLOCK | on-chip | clock and reset control | 139+-----------+------------+-------------------------------------+ 140| GPIO | on-chip | gpio | 141+-----------+------------+-------------------------------------+ 142| UART | on-chip | serial | 143+-----------+------------+-------------------------------------+ 144| TRNG | on-chip | entropy | 145+-----------+------------+-------------------------------------+ 146| I2C | on-chip | i2c | 147+-----------+------------+-------------------------------------+ 148| DMA | on-chip | dma controller | 149+-----------+------------+-------------------------------------+ 150| Watchdog | on-chip | watchdog | 151+-----------+------------+-------------------------------------+ 152| SPI | on-chip | spi | 153+-----------+------------+-------------------------------------+ 154| ADC | on-chip | adc | 155+-----------+------------+-------------------------------------+ 156| Timer | on-chip | counter | 157+-----------+------------+-------------------------------------+ 158| PWM | on-chip | pwm | 159+-----------+------------+-------------------------------------+ 160| W1 | on-chip | one wire master | 161+-----------+------------+-------------------------------------+ 162| Flash | on-chip | flash | 163+-----------+------------+-------------------------------------+ 164 165Connections and IOs 166=================== 167 168+-----------+-------------------+----------------------------------------------------------------------------------+ 169| Name | Signal | Usage | 170+===========+===================+==================================================================================+ 171| JP1 | 3V3 MON | Normal operation in conjunction with JP3 jumpered 1-2 | 172+-----------+-------------------+----------------------------------------------------------------------------------+ 173| JP2 | 3V3 SW PM BYPASS | Power monitor shunts for main 3.3 V system power are bypassed | 174+-----------+-------------------+----------------------------------------------------------------------------------+ 175| JP3 | CNN MON | Normal operation in conjunction with JP6 jumpered 1-2 | 176+-----------+-------------------+----------------------------------------------------------------------------------+ 177| JP4 | VCOREA PM BYPASS | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed | 178+-----------+-------------------+----------------------------------------------------------------------------------+ 179| JP5 | VCOREB PM BYPASS | Power monitor shunts for VCOREB are bypassed | 180+-----------+-------------------+----------------------------------------------------------------------------------+ 181| JP6 | VREGO_A PM BYPASS | Power monitor shunts for VREGO_A are bypassed | 182+-----------+-------------------+----------------------------------------------------------------------------------+ 183| JP7 | VBAT | Enable/Disable 3V3 VBAT power | 184+-----------+-------------------+----------------------------------------------------------------------------------+ 185| JP8 | VREGI | Enable/Disable 3V3 VREGI power | 186+-----------+-------------------+----------------------------------------------------------------------------------+ 187| JP9 | VREGI/VBAT | Onboard 3V3_PM / external source at TP10 supplies VREGI/VBAT | 188+-----------+-------------------+----------------------------------------------------------------------------------+ 189| JP10 | VDDIOH | Onboard 3V3_PM/3V3_SW supplies VDDIOH | 190+-----------+-------------------+----------------------------------------------------------------------------------+ 191| JP11 | VDDA | VREGO_A_PM powers VDDA | 192+-----------+-------------------+----------------------------------------------------------------------------------+ 193| JP12 | VDDIO | VREGO_A_PM powers VDDIO | 194+-----------+-------------------+----------------------------------------------------------------------------------+ 195| JP13 | VCOREB | VREGO_B powers VCOREB | 196+-----------+-------------------+----------------------------------------------------------------------------------+ 197| JP14 | VCOREA | VREGO_C ties to net VCOREA | 198+-----------+-------------------+----------------------------------------------------------------------------------+ 199| JP15 | VREF | DUT ADC VREF is supplied by precision external reference | 200+-----------+-------------------+----------------------------------------------------------------------------------+ 201| JP16 | I2C1 SDA | I2C1 DATA pull-up | 202+-----------+-------------------+----------------------------------------------------------------------------------+ 203| JP17 | I2C1 SCL | I2C1 CLOCK pull-up | 204+-----------+-------------------+----------------------------------------------------------------------------------+ 205| JP18 | TRIG1 | PWR accumulator trigger signal 1 ties to port 1.6 | 206+-----------+-------------------+----------------------------------------------------------------------------------+ 207| JP19 | TRIG2 | PWR accumulator trigger signal 2 ties to port 1.7 | 208+-----------+-------------------+----------------------------------------------------------------------------------+ 209| JP20 | UART0 EN | Connect/Disconnect USB-UART bridge to UART0 | 210+-----------+-------------------+----------------------------------------------------------------------------------+ 211| JP21 | I2C0_SDA | I2C0 DATA pull-up | 212+-----------+-------------------+----------------------------------------------------------------------------------+ 213| JP22 | I2C0_SCL | I2C0 CLOCK pull-up | 214+-----------+-------------------+----------------------------------------------------------------------------------+ 215| JP23 | UART1 EN | Connect/Disconnect USB-UART bridge to UART1 | 216+-----------+-------------------+----------------------------------------------------------------------------------+ 217| JP24 | EXT I2C0 EN | Enable/Disable QWIIC interface for I2C0 | 218+-----------+-------------------+----------------------------------------------------------------------------------+ 219| JP25 | PB1 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.6 | 220+-----------+-------------------+----------------------------------------------------------------------------------+ 221| JP26 | PB2 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.7 | 222+-----------+-------------------+----------------------------------------------------------------------------------+ 223| JP27 | I2C2 SDA | I2C2 DATA pull-up | 224+-----------+-------------------+----------------------------------------------------------------------------------+ 225| JP28 | I2C2 SCL | I2C2 CLOCK pull-up | 226+-----------+-------------------+----------------------------------------------------------------------------------+ 227| JP29 | VDDB | USB XCVR VDDB powered from VBUS / powered full time by system 3V3_PM | 228+-----------+-------------------+----------------------------------------------------------------------------------+ 229| JP30 | EXT I2C2 EN | Enable/Disable QWIIC interface for I2C2 | 230+-----------+-------------------+----------------------------------------------------------------------------------+ 231| JP31 | L/R SEL | Select MIC ON R/L CH, I2S microphone data stream | 232+-----------+-------------------+----------------------------------------------------------------------------------+ 233| JP32 | MIC-I2S I/O | External I2S/MIC data from I2S I/O / MIC header connected to I2S SDI | 234+-----------+-------------------+----------------------------------------------------------------------------------+ 235| JP33 | MIC-I2S/CODEC | Onboard CODEC data / external I2S data from header connects to I2S SDI | 236+-----------+-------------------+----------------------------------------------------------------------------------+ 237| JP34 | I2S VDD | Select 1.8V/3.3V for external MIC and DATA I2S interface | 238+-----------+-------------------+----------------------------------------------------------------------------------+ 239| JP35 | I2C1 SDA | I2C1 DATA pull-up | 240+-----------+-------------------+----------------------------------------------------------------------------------+ 241| JP36 | I2C1 SCL | I2C1 CLOCK pull-up | 242+-----------+-------------------+----------------------------------------------------------------------------------+ 243| JP37 | I2S CK SEL | Select SMA connector J6 / onboard crystal oscillator for I2S master clock source | 244+-----------+-------------------+----------------------------------------------------------------------------------+ 245| JP38 | DVP CAM PWR | Enable/Disable OVM7692 for DVP camera PWDN input | 246+-----------+-------------------+----------------------------------------------------------------------------------+ 247| JP39 | SW CAM PWUP | Camera reset and power up under port pin control | 248+-----------+-------------------+----------------------------------------------------------------------------------+ 249| JP40 | HW PWUP / SW PWUP | Camera will reset and power up as soon as 3.3V reaches a valid level | 250+-----------+-------------------+----------------------------------------------------------------------------------+ 251| JP41 | CSI CAM I2C EN | Connect/Disconnect I2C1 to CSI camera Digilent P5C I2C | 252+-----------+-------------------+----------------------------------------------------------------------------------+ 253| JP42 | TFT DC | TFT data/command select connects to port 2.2 | 254+-----------+-------------------+----------------------------------------------------------------------------------+ 255| JP43 | TFT CS | Select port 0.3 / port 1.7 to drive TFT CS | 256+-----------+-------------------+----------------------------------------------------------------------------------+ 257| JP44 | LED1 EN | Enable/Disable LED1 | 258+-----------+-------------------+----------------------------------------------------------------------------------+ 259| JP45 | LED2 EN | Enable/Disable LED2 | 260+-----------+-------------------+----------------------------------------------------------------------------------+ 261 262Programming and Debugging 263************************* 264 265Flashing 266======== 267 268The MAX78002 MCU can be flashed by connecting an external debug probe to the 269SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH8. 270Logic levels are fixed to VDDIO (1.8V). 271 272Once the debug probe is connected to your host computer, then you can simply run the 273``west flash`` command to write a firmware image into flash. 274 275.. note:: 276 277 This board uses OpenOCD as the default debug interface. You can also use 278 a Segger J-Link with Segger's native tooling by overriding the runner, 279 appending ``--runner jlink`` to your ``west`` command(s). The J-Link should 280 be connected to the standard 2*5 pin debug connector (JH8) using an 281 appropriate adapter board and cable. 282 283Debugging 284========= 285 286Please refer to the `Flashing`_ section and run the ``west debug`` command 287instead of ``west flash``. 288 289References 290********** 291 292- `MAX78002EVKIT web page`_ 293 294.. _MAX78002EVKIT web page: 295 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html 296
