Searched refs:bits (Results 226 – 250 of 680) sorted by relevance
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| /Zephyr-latest/samples/subsys/ipc/openamp/ |
| D | README.rst | 64 - Data: 8 bits
66 - Stop bits: 1
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | dai-params-intel-ipc4.h | 176 } bits; /**<< Bits */ member
187 struct bits { struct
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| /Zephyr-latest/boards/atmel/sam0/samr34_xpro/doc/ |
| D | index.rst | 139 of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is
179 - Data: 8 bits
181 - Stop bits: 1
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| /Zephyr-latest/dts/arm/nordic/ |
| D | nrf52811.dtsi | 147 easydma-maxcnt-bits = <14>;
167 easydma-maxcnt-bits = <14>;
185 easydma-maxcnt-bits = <14>;
270 length-field-length-8-bits;
400 arm,num-irq-priority-bits = <3>;
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| D | nrf52805.dtsi | 131 easydma-maxcnt-bits = <14>;
150 easydma-maxcnt-bits = <14>;
235 length-field-length-8-bits;
340 arm,num-irq-priority-bits = <3>;
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| D | nrf52810.dtsi | 135 easydma-maxcnt-bits = <10>;
154 easydma-maxcnt-bits = <10>;
238 length-field-length-8-bits;
365 arm,num-irq-priority-bits = <3>;
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| D | nrf5340_cpunet.dtsi | 157 length-field-length-8-bits;
205 easydma-maxcnt-bits = <16>;
223 easydma-maxcnt-bits = <16>;
363 arm,num-irq-priority-bits = <3>;
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| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/ |
| D | npcx9-miwus-wui-map.dtsi | 12 /* Mapping between MIWU wui bits and source device */
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| /Zephyr-latest/drivers/dai/intel/alh/ |
| D | alh.h | 66 } bits; /**<< Bits */ member
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| /Zephyr-latest/boards/arm/v2m_musca_b1/ |
| D | v2m_musca_b1_musca_b1_ns.dts | 72 arm,num-irq-priority-bits = <3>;
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| /Zephyr-latest/scripts/build/ |
| D | gen_cfb_font_header.py | 62 bits = []
64 bits.append(value)
68 args.output.write(" /* {} */\n".format(''.join(bits).replace('0', ' ').replace('1', '#')))
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| /Zephyr-latest/doc/kernel/services/other/ |
| D | atomic.rst | 76 The following code shows how a set of 200 flag bits can be implemented
109 on a set of flag bits in a bit array longer than 32 bits.
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| /Zephyr-latest/dts/arm/nuvoton/npcm/ |
| D | npcm.dtsi | 52 arm,num-irq-priority-bits = <3>;
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| /Zephyr-latest/modules/liblc3/ |
| D | CMakeLists.txt | 28 ${ZEPHYR_LIBLC3_MODULE_DIR}/src/bits.c
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| /Zephyr-latest/boards/arm/v2m_musca_s1/ |
| D | v2m_musca_s1_musca_s1_ns.dts | 72 arm,num-irq-priority-bits = <3>;
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| /Zephyr-latest/samples/drivers/ipm/ipm_mhu_dual_core/ |
| D | README.rst | 60 - Data: 8 bits
62 - Stop bits: 1
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| /Zephyr-latest/boards/ambiq/apollo4p_evb/doc/ |
| D | index.rst | 74 - Data: 8 bits
76 - Stop bits: 1
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| /Zephyr-latest/boards/ambiq/apollo3_evb/doc/ |
| D | index.rst | 71 - Data: 8 bits
73 - Stop bits: 1
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| /Zephyr-latest/boards/ambiq/apollo3p_evb/doc/ |
| D | index.rst | 71 - Data: 8 bits
73 - Stop bits: 1
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| /Zephyr-latest/boards/atmel/sam0/samr21_xpro/doc/ |
| D | index.rst | 97 period of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then
192 - Data: 8 bits
194 - Stop bits: 1
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| /Zephyr-latest/boards/atmel/sam0/same54_xpro/doc/ |
| D | index.rst | 150 of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is
197 - Data: 8 bits
199 - Stop bits: 1
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| /Zephyr-latest/doc/hardware/peripherals/can/ |
| D | controller.rst | 22 state for at least 11 recessive bits. Therefore you have to make sure that
67 They resolve by the fact that dominant bits override recessive bits.
77 As an example, a mask with 11 bits set for standard or 29 bits set for extended
88 dominant bits, which is a violation of the stuffing rule that all nodes can
104 bus-off state. In this state, the node is not allowed to send any dominant bits
106 occurrences of 11 concurrent recessive bits.
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.clic | 35 hardware vectoring is set via mode bits of mtvec.
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| /Zephyr-latest/drivers/w1/ |
| D | Kconfig.zephyr_serial | 28 complete, it must at least be greater than 87us (10bits / 115.2 kBd).
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| /Zephyr-latest/drivers/watchdog/ |
| D | Kconfig.it8xxx2 | 11 This driver supports only one channel that id is 0 and 16-bits
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