1/*
2 * Copyright (c) 2024 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8
9/* Macros for device tree declarations of npcm soc family */
10#include <zephyr/dt-bindings/clock/npcm_clock.h>
11#include <freq.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-m4";
21			reg = <0>;
22		};
23	};
24
25	soc {
26		mdc: mdc@4000c000 {
27			compatible = "syscon";
28			reg = <0x4000c000 0xa>;
29			reg-io-width = <1>;
30		};
31
32		mdc_header: mdc@4000c00a {
33			compatible = "syscon";
34			reg = <0x4000c00a 0x4>;
35			reg-io-width = <2>;
36		};
37
38		pcc: clock-controller@4000d000 {
39			compatible = "nuvoton,npcm-pcc";
40			/* Cells for clock id */
41			#clock-cells = <1>;
42			/* First reg region is Power Management Controller */
43			/* Second reg region is Core Domain Clock Generator */
44			reg = <0x4000d000 0x2000
45				   0x400b5000 0x2000>;
46			reg-names = "pmc", "cdcg";
47		};
48	};
49};
50
51&nvic {
52	arm,num-irq-priority-bits = <3>;
53};
54