1/*
2 * Copyright (c) 2019 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <arm/armv8-m.dtsi>
10
11/ {
12	compatible = "arm,v2m-musca";
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	aliases {
17	};
18
19	chosen {
20		zephyr,console = &uart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,shell-uart = &uart1;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu@0 {
31			device_type = "cpu";
32			compatible = "arm,cortex-m33";
33			reg = <0>;
34			#address-cells = <1>;
35			#size-cells = <1>;
36
37			mpu: mpu@e000ed90 {
38				compatible = "arm,armv8m-mpu";
39				reg = <0xe000ed90 0x40>;
40			};
41		};
42	};
43
44	flash0: flash@a070000 {
45		/* Embedded flash */
46		reg = <0xa070000 0x1a0000>;
47	};
48
49	sram0: memory@20040000 {
50		compatible = "mmio-sram";
51		reg = <0x20040000 0x40000>;
52	};
53
54	sysclk: system-clock {
55		compatible = "fixed-clock";
56		clock-frequency = <40000000>;
57		#clock-cells = <0>;
58	};
59
60	soc {
61		peripheral@40000000 {
62			#address-cells = <1>;
63			#size-cells = <1>;
64			ranges = <0x0 0x40000000 0x10000000>;
65
66			#include "v2m_musca_b1-common.dtsi"
67		};
68	};
69};
70
71&nvic {
72	arm,num-irq-priority-bits = <3>;
73};
74