| /Zephyr-latest/dts/bindings/spi/ |
| D | nxp,imx-flexspi.yaml | 1 # Copyright 2018-2023, NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-flexspi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 ahb-bufferable:
23 ahb-cacheable:
29 ahb-prefetch:
34 ahb-read-addr-opt:
40 combination-mode:
43 Combine port A and port B data pins to support octal mode access by
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| D | atmel,sam0-spi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-spi"
9 - name: spi-controller.yaml
10 - name: pinctrl-device.yaml
19 clock-names:
34 Optional TX & RX dma specifiers. Each specifier will have a phandle
36 trigger source.
38 For example dmas for TX, RX on SERCOM3
41 dma-names:
43 Required if the dmas property exists. This should be "tx" and "rx"
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| /Zephyr-latest/drivers/ethernet/nxp_enet/ |
| D | Kconfig | 3 # Copyright (c) 2016-2017 ARM Ltd
5 # SPDX-License-Identifier: Apache-2.0
62 - IPv4, UDP and TCP checksum (both Rx and Tx)
65 int "Number of RX buffers for ethernet driver"
69 Set the number of RX buffers provided to the NXP ENET driver.
79 int "NXP ENET RX thread stack size"
82 ENET RX thread stack size in bytes.
85 int "NXP ENET driver RX cooperative thread priority"
88 ENET MAC Driver handles RX in cooperative workqueue thread.
113 - IPv4, UDP and TCP checksum (both Rx and Tx)
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | atmel,sam0-i2c.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-i2c"
9 - name: i2c-controller.yaml
10 - name: pinctrl-device.yaml
22 clock-names:
27 Optional TX & RX dma specifiers. Each specifier will have a phandle
29 trigger source.
31 For example dmas for TX, RX on SERCOM3
34 dma-names:
36 Required if the dmas property exists. This should be "tx" and "rx"
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| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.stm32_hal | 5 # SPDX-License-Identifier: Apache-2.0
43 int "RX thread stack size"
46 RX thread stack size
49 int "STM32 Ethernet RX Thread Priority"
52 This option allows to configure the priority of the RX thread that
83 Set the RX idle timeout period in milliseconds after which the
84 PHY's carrier status is re-evaluated.
93 bool "Use TX and RX hardware checksum"
119 bool "STM32 HAL PTP clock driver support"
123 Enable STM32 PTP clock support.
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| /Zephyr-latest/dts/bindings/serial/ |
| D | renesas,smartbond-uart.yaml | 3 compatible: "renesas,smartbond-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
14 periph-clock-config:
16 description: Peripheral clock register configuration (COM domain)
19 current-speed:
21 Initial baud rate setting for UART. Only a fixed set of baud
24 - 4800
25 - 9600
26 - 14400
27 - 19200
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| /Zephyr-latest/drivers/serial/ |
| D | uart_stm32.h | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
32 /* clock subsystem driving this peripheral */
34 /* number of clock subsystems */
38 /* enable tx/rx pin swap */
40 /* enable rx pin inversion */
46 /* de signal assertion time in 1/16 of a bit */
48 /* de signal deassertion time in 1/16 of a bit */
61 /* Device defined as wake-up source */
89 /* clock device */
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| D | uart_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
50 /* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */ in uart1_wui_isr()
51 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart1_wui_isr()
54 /* Refresh console expired time if got UART Rx wake-up event */ in uart1_wui_isr()
63 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart1_wui_isr()
70 /* Disable interrupts on UART2 RX pin to avoid repeated interrupts. */ in uart2_wui_isr()
71 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart2_wui_isr()
74 /* Refresh console expired time if got UART Rx wake-up event */ in uart2_wui_isr()
83 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart2_wui_isr()
90 const struct uart_it8xxx2_config *const config = dev->config; in uart_it8xxx2_pm_action()
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| /Zephyr-latest/dts/bindings/qspi/ |
| D | nxp,s32-qspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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| /Zephyr-latest/doc/build/dts/ |
| D | dt-vs-kconfig.rst | 7 source code. Whether to use devicetree or Kconfig for a particular purpose can
12 * Use devicetree to describe **hardware** and its **boot-time configuration**.
13 Examples include peripherals on a board, boot-time clock frequencies,
22 For example, consider a board containing a SoC with 2 UART, or serial port,
29 * Additionally, the UART **boot-time configuration** is also described with
30 devicetree. This could include configuration such as the RX IRQ line's
32 their boot-time configuration is described in devicetree.
35 remove the driver source code from the build using Kconfig, even though the
38 As another example, consider a device with a 2.4GHz, multi-protocol radio
43 * **Boot-time configuration** for the radio, such as TX power in dBm, should
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_k6x.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
4 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/adc.h>
6 #include <zephyr/dt-bindings/clock/kinetis_sim.h>
7 #include <zephyr/dt-bindings/clock/kinetis_mcg.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
18 zephyr,flash-controller = &ftfe;
22 #address-cells = <1>;
23 #size-cells = <0>;
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| D | nxp_rt10xx.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
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| D | nxp_ke1xf.dtsi | 2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/kinetis_pcc.h>
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
20 zephyr,flash-controller = &ftfe;
24 #address-cells = <1>;
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| D | nxp_rt1010.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
10 flexram,num-ram-banks = <4>;
12 flexram,bank-spec = <FLEXRAM_OCRAM>,
19 clock-frequency = <500000000>;
35 /delete-node/ arm-podf;
37 ipg-podf {
38 clock-div = <4>;
61 irq-shared-offset = <0>;
62 dma-channels = <16>;
67 /* Remove GPIO3-GPIO9, they don't exist on RT1010 */
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| D | nxp_mcxn23x_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
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| /Zephyr-latest/drivers/dai/nxp/sai/ |
| D | sai.h | 3 * SPDX-License-Identifier: Apache-2.0
31 * to also take a variable number of arguments.
35 /* used to generate the list of clock indexes */
39 /* used to retrieve a clock's ID using its index generated via _SAI_CLOCK_INDEX_ARRAY */
43 /* used to retrieve a clock's name using its index generated via _SAI_CLOCK_INDEX_ARRAY */
47 /* used to convert the clocks property into an array of clock IDs */
51 /* used to convert the clock-names property into an array of clock names */
55 /* used to convert a clocks property into an array of clock IDs. If the property
63 /* used to retrieve a const struct device *dev pointing to the clock controller.
64 * It is assumed that all SAI clocks come from a single clock provider.
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| D | sai.c | 4 * SPDX-License-Identifier: Apache-2.0
26 * 2) The SAI ISR should stop the SAI whenever a FIFO error interrupt
35 * register. As such, the MCLK source field of sai_master_clock_t is
36 * useless. I'm assuming the source is selected through xCR2's MSEL.
40 * generating BCLK. Is there a need to support different MCLKs in
53 cfg = dev->config; in sai_mclk_config()
54 data = dev->data; in sai_mclk_config()
56 mclk_config.mclkOutputEnable = cfg->mclk_is_output; in sai_mclk_config()
60 LOG_ERR("invalid MCLK source %d for MSEL", bclk_source); in sai_mclk_config()
65 ret = get_mclk_rate(&cfg->clk_data, bclk_source, &mclk_rate); in sai_mclk_config()
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| /Zephyr-latest/boards/nxp/mimxrt595_evk/ |
| D | mimxrt595_evk_mimxrt595s_cm33.dts | 2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi"
16 model = "NXP MIMXRT595-EVK board";
25 usart-0 = &flexcomm0;
30 pwm-0 = &sc_timer;
31 dmic-dev = &dmic0;
32 mcuboot-button0 = &user_button_1;
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| /Zephyr-latest/drivers/i2s/ |
| D | i2s_nrfx.c | 4 * SPDX-License-Identifier: Apache-2.0
33 struct stream_cfg rx; member
39 bool stop; /* stop after the current (TX or RX) block */
40 bool discard_rx; /* discard further RX blocks */
59 /* Finds the clock settings that give the frame clock frequency closest to
81 (NRF_I2S_HAS_CLKCONFIG && drv_cfg->clk_src == ACLK) in find_suitable_clock()
83 * make sure that the ACLK clock source is only used when it is in find_suitable_clock()
84 * available and only with the "hfclkaudio-frequency" property in find_suitable_clock()
89 ? DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, 0) in find_suitable_clock()
91 uint32_t bits_per_frame = 2 * i2s_cfg->word_size; in find_suitable_clock()
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| /Zephyr-latest/drivers/ethernet/phy/ |
| D | phy_dm8806_priv.h | 4 * SPDX-License-Identifier: Apache-2.0
63 /* Read a entry with sequence number of address table */
65 /* Write a entry with MAC address */
67 /* Delete a entry with MAC address */
69 /* Search a entry with MAC address */
131 /* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5
135 /* Port 5 Clock Source Selection control bit. Only available when Port 5
145 * 100M link fail - LED off
146 * 100M link ok and no TX/RX activity - LED on
147 * 100M link ok and TX/RX activity - LED blinking
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| /Zephyr-latest/samples/boards/96boards/argonkey/microphone/ |
| D | README.rst | 1 .. zephyr:code-sample:: argonkey_microphone
3 :relevant-api: audio_interface
5 Acquire audio through the ArgonKey's on-board MP34DT05 microphone.
10 the on-board MP34DT05 microphone. The microphone generates a PDM
13 in source code in this sample.
18 This sample requires the ArgonKey board plus a USB to TTL 1V8 serial
22 - mezzanine mode, plugging the ArgonKey to HiKey board through its 96Board
23 low-speed connector
24 - standalone mode, supplying 5V directly on P1 connector
29 - :ref:`96b_argonkey`
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| /Zephyr-latest/boards/st/sensortile_box/doc/ |
| D | index.rst | 6 The STEVAL-MKSBOX1V1 (SensorTile.box) is a ready-to-use box kit for wireless
9 The SensorTile.box board fits into a small plastic box with a long-life rechargeable
10 battery, and communicates with a standard smartphone through its Bluetooth interface,
20 - Ultra low-power STM32L4R9ZI System on Chip
22 - LQFP144 package
23 - Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive
24 real-time accelerator (ART Accelerator) allowing 0-wait-state
27 - Clock Sources:
29 - 16 MHz crystal oscillator
30 - 32 kHz crystal oscillator for RTC (LSE)
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| /Zephyr-latest/boards/nxp/mr_canhubk3/ |
| D | mr_canhubk3.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
17 model = "NXP MR-CANHUBK3";
25 zephyr,code-partition = &code_partition;
27 zephyr,shell-uart = &lpuart2;
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| /Zephyr-latest/boards/st/stm32g081b_eval/ |
| D | stm32g081b_eval.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g0/stm32g081rbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,stm32g081-eval";
18 zephyr,shell-uart = &usart3;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
83 volt-sensor0 = &vref;
84 volt-sensor1 = &vbat;
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | ssp.c | 4 * SPDX-License-Identifier: Apache-2.0
22 #define dai_set_drvdata(dai, data) (dai->priv_data = data)
23 #define dai_get_drvdata(dai) dai->priv_data
24 #define dai_get_plat_data(dai) dai->ssp_plat_data
25 #define dai_get_mn(dai) dai->ssp_plat_data->mn_inst
26 #define dai_get_ftable(dai) dai->ssp_plat_data->ftable
27 #define dai_get_fsources(dai) dai->ssp_plat_data->fsources
28 #define dai_mn_base(dai) dai->ssp_plat_data->mn_inst->base
29 #define dai_base(dai) dai->ssp_plat_data->base
30 #define dai_ip_base(dai) dai->ssp_plat_data->ip_base
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